Abstract: A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium.

Abstract: An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

Abstract: An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

Abstract: A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data between the first and second circuit portions. The clock circuitry generates a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge, and a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge. A change in the relative frequency is conditional on a coincidence of the first and second control signals. The synchronisation generates the pulses such that there is at least one cycle of the first clock signal between those pulses, and such that there is only one of those pulses per cycle of the second clock signal.

Abstract: A method of processing a signal in a wireless digital communications system, wherein a source of disturbance affects differently at least first and second portions of a received signal carrying user data and/or control data, the method comprising: identifying the second portion of the received signal, most affected by the source of disturbance; generating a first estimate of the disturbance (PI) for received samples in the first, less affected portion of the received signal; generating a second estimate of the disturbance (PI(SCH)) for received samples in the second portion of the received signal; and using the first and second disturbance estimates to generate reliability information for the data bits corresponding to the received signal samples, for use in a decoding process to estimate the transmitted data bits.

Abstract: An apparatus and method is disclosed for decoding a received sequence of symbols using a decoding process that comprises a plurality of decoder iterations. According to one embodiment of the invention, a method comprises determining whether a pre-determined decoder termination threshold metric has been met; only if the threshold metric has been met, determining whether a decoder termination test based on a cyclic redundancy check code has been passed; and, only if the cyclic redundancy check test has been passed, terminating the decoder iterations.

Abstract: A decoder for use in a wireless communication device, the decoder comprising a correlator for correlating a received data sequence with a set of codewords such that a correlation value is generated for each correlation, wherein the set of codewords correspond to possible codewords that could be generated from encoding bit sequences having a predetermined number of information bits; a selector for selecting a first correlation value and a second correlation value generated by the correlator and for subtracting the second correlation value from the first correlation value to generate a third value; and a comparator for comparing the third value with a predetermined value to generate a decoding reliability indicator.

Abstract: A method for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch of the interconnect layout and a transistor pitch of the logic cell. The cell grid is aligned with the resized routing pitch which provides efficient routing density and transistor performance, minimizes excess transistor area and wire routing waste while maximizing cell packing density.

Abstract: A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.

Abstract: A method (150) for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell (12) is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch (24) of the interconnect layout and a transistor pitch (14) of the logic cell. The cell grid is aligned with the resized routing pitch (124) which provides efficient routing density and transistor performance, minimises excess transistor area and wire routing waste while maximising cell packing density.

Abstract: A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.

Abstract: Logic cell layout architecture having a shared boundary between at least two cells each forming logic functions, and a method (200) for designing a logic cell library having a shared boundary between at least two cells (12,32) is disclosed for increasing packing density and limiting the occurrence of stress between active areas and shallow trench isolation (STI) regions of logic cells within a standard cell library for semiconductor integrated circuits (IC).

Abstract: A system (10,90), apparatus (12,30,40,50,60,70) and method (100) is disclosed for detecting excess current leakage between drain/source of a metal oxide semiconductor (MOS) transistor (36,46) within a complementary MOS (CMOS) environment. A load control (32,42) is arranged as a compliment to the MOS transistor. A comparator (34,44) is electrically connected to the load control and the MOS transistor, and produces an output signal representative of the detection of a current leakage exceeding a threshold. In response to the received output signal indicating an excess current leakage, system voltage/frequency may be adjusted to prevent damage to the CMOS environment.