Abstract: A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch while one or more others perform a transfer.

Abstract: A method, program and apparatus for transmitting an RF signal over a wireless communication network. The method comprises: determining a respective weighting factor for each of a plurality of digital signals each corresponding to a respective channel, the weighting factors being for weighting the digital signals for combination to produce a composite signal intended for transmission as an RF signal via a power amplifier. The method further comprises: executing instructions on a processor to dynamically calculate, in the processor, a metric related to the non-linearity of the power amplifier's transfer characteristics for the composite signal using the determined weighting factors; supplying to the power amplifier a signal for transmission as an RF signal; amplifying the signal for transmission at the power amplifier to transmit an RF signal over the wireless communication network via at least one antenna; and controlling the transmission based on the metric related to the amplifier non-linearity.

Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.

Abstract: A method and system for fractionally converting sample rates. Fractional rate conversion for a transmit path of a transceiver is achieved by upsampling an input signal having a first sample rate by a first integer factor, removing aliasing resulting from the upconversion process, and then downsampling the intermediate signal by a second integer factor to provide a final signal having a second sample rate. The first factor and the second factor are selected to obtain a desired output sample rate that is a fraction of the sample rate of the input signal.

Abstract: A design process optimization system and method for designing a circuit, which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit.

Abstract: According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer.

Abstract: The present invention relates to a method of transmitting channel quality data for channels in a wireless communication system, and to a corresponding receiver and transmitter. The method comprises determining a plurality of channel quality indicators for a corresponding plurality of frequency intervals, and transmitting information about channel quality indicators in the form of differentially encoded slope data.

Abstract: According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.

Abstract: According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer.

Abstract: Method and receiver for processing a signal in a wireless communication system in which the signal comprises a sequence of chips. The signal is receive data at least one rake finger and sampled. There is a time spacing t1 between successive samples less than the time spacing tc between successive chips in the signal. Channel conditions on the channel are estimated and based on estimated channel conditions by the following steps: monitoring timing of the signal on one of the at least one rake finger to determine a time difference between the timing of the signal on the one of the at least one rake finger and the timing of the generation of the samples, the determined time difference being a multiple of t2, where t2<t1; aligning the timing of the generation of the samples with the timing of the signal on the one of the at least one rake finger to within a timing range t2.

Abstract: A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions. The processing channel comprises a plurality of functional units and operable to perform control processing operations. The decode unit is operable to receive and decode instruction packets of a bit length of 64 bits and to detect if the instruction packet defines three control instructions each having a length of 21 bits. The decode unit detects that the instruction packet comprises the three control instructions. The control instructions are supplied to the processing channel for execution in the order in which they appear in the instruction packet. The detection uses an identification bit in the instruction packet.

Abstract: A method and apparatus for processing a signal in a wireless communication system. The method comprises: receiving a signal at a receiver over a wireless channel; sampling the signal to produce a plurality of signal samples; and supplying the samples to an equaliser implemented in software running on a processor of the receiver, the equaliser being configured to process the samples using at least one equaliser time period having a nominal length. The method further comprises dynamically determining one or more characteristics of the channel; in dependence on the determined channel characteristics, dynamically selecting between a first operational state of the equaliser in which the nominal length is used and a second operational state of the equaliser in which an alternative length is used in place of the nominal length; and processing the samples in the equaliser using the determined equaliser time period length.

Abstract: A method, program and system for transmitting from a transmitter to a receiver over a wireless multipie-input-multiple-output channel. In one aspect, the method may comprise encoding precoding information fed back from the receiver to the transmitter according to a differential encoding scheme, and resetting the differential encoding scheme upon detecting a condition. In another aspect, the method may comprises encoding precoding matrices fed back from the receiver to the transmitter relative to a most-probable subset of precoding matrices. In another aspect, the method may comprise transmitting an indication of and/or the size of a preferred subset of precoding matrices for use in the encoding.

Abstract: In one aspect, there is provided a method of processing a signal received using a wireless communication channel by a receiver in a wireless cellular network. In one embodiment, the method comprises receiving signal samples of a signal to be processed from a serving cell, identifying a second of dominant interfering cells generating an interfering signal, using a number of cells in the set to select an interference scenario, and using the selected interference scenario and at least one parameter related to the serving cell and the interfering cells to select a processing function for processing the signal.

Abstract: A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least one of them having an output arranged to supply the logical output of the latch. Each of the differential amplifiers includes a transistor connected as a load, and an output of each of the differential amplifiers is coupled to bias the load transistor of the other differential amplifier. If the latch switches from the transparent state to the closed state while the logical input signal is transitioning between logical levels, the differential amplifiers drive up the logical output of the latch if the logical input signal transitions from a first to a second logical level, and drive down the logical output of the latch if the input signal transitions from the second to the first logical level.

Abstract: A circuit for converting a lower voltage logical signal to a higher voltage. The circuit comprises a current mirror structure having first and second branches, each comprising at least a first transistor of a first kind, an input transistor of a second kind, and a second transistor of the first kind coupled between them. The first transistors are arranged as a current mirror. The input transistors are driven using a logical signal at the lower voltage, controlling the current mirror structure to output a corresponding logical signal at the higher voltage. The second transistors are driven by an intermediate reference voltage so as to reduce the operating voltage of the third transistors. The first kind is tolerant of a higher operating voltage than the second kind.

Abstract: A system and method for processing digital samples from a signal received via a wireless transmission channel in a wireless communications system. The method comprises: comparing a target signal quality value with an estimated received signal quality value; detecting if the estimated received signal quality value exceeds the target signal quality value for a period; and selecting one of a plurality of processing routines of differing sensitivities for processing the digital samples.

Abstract: A method of power control in a wireless communication system wherein blocks are transmitted from a transmitter to a receiver on multiple wireless transport channels. The method comprises comparing a target signal quality value with a received signal quality value and providing the results of the comparing step to the transmitter to adjust transmit power, and a mechanism for controlling the target signal quality for transport channels that have been inactive for a predefined period. A corresponding receiver is also provided.

Abstract: The present invention provides a method of estimating a frequency offset. The method comprises receiving a wireless signal timed according to a first frequency; generating a local signal timed according to a second frequency; and performing a plurality of synchronization searches, each search comprising obtaining a set of correlation results indicative of a correlation between the wireless signal and the local signal at different timing offsets of the wireless signal relative to the local signal. The method the no comprises finding a series of results, with a result from each of a plurality of the synchronization searches, for which the difference in; timing offset between results from adjacent searches in the series is within a maximum specified value. A frequency off set between the first and second frequencies can be determined from the series.

Abstract: A decoder for use in a wireless communication device, the decoder comprising a correlator for correlating a received data sequence with a set of codewords such that a correlation value is generated for each correlation, wherein the set of codewords correspond to possible codewords that could be generated from encoding bit sequences having a predetermined number of information bits; a selector for selecting a first correlation value and a second correlation value generated by the correlator and for subtracting the second correlation value from the first correlation value to generate a third value; and a comparator for comparing the third value with a predetermined value to generate a decoding reliability indicator.