Abstract: Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value.

Abstract: A circuit and method for determining the frequency of a first oscillating reference signal generated by a first reference oscillator. The circuit comprises: a second reference oscillator arranged to generate a second oscillating reference signal having a known frequency, a boot memory storing boot code comprising clock configuration code, and a processor coupled to the boot memory and the second reference oscillator. The processor is arranged to execute the boot code from the boot memory upon booting, wherein when executed the clock configuration code operates the processor to determine the frequency of the first reference signal by reference to the second reference signal.

Abstract: A method, receiver and program for equalising a radio signal comprising a sequence of data samples multiplexed with a sequence of pilot samples. The method comprises; calculating equaliser coefficients by computing cross-correlations of the received signal and known pilot samples available at the receiver and auto-correlations of the received signal; and equalising the received signal using the calculated coefficients.

Abstract: A method, receiver and program for processing a signal received using a wireless communication channel by a receiver in a wireless cellular network. The method comprises: receiving signal samples of a signal to be processed from a serving cell; identifying a set of dominant interfering cells generating an interfering signal above a level; using the number of cells in the set to select an interference scenario; and using the selected interference scenario and at least one parameter related to the serving cell and the interfering cells to select a processing function for processing the signal.

Abstract: The present invention provides a processor comprising: an execution unit arranged to execute a plurality of program threads, clock generating means for generating first and second clock signals, and storage means for storing at least one thread-specific clock-control bit. The execution unit is configured to execute a first one of the threads in dependence on the first clock signal and to execute a second one of the threads in dependence on the second clock signal. The clock generating means is operable to generate the second clock signal with the second frequency selectively differing from the first frequency in dependence on the at least one clock-control bit. A corresponding method and computer program product are also provided.

Abstract: A method, receiver and program for equalising digital samples of a radio signal received over a wireless communications channel. The method comprises: receiving digital samples of the radio signal; calculating equaliser coefficients in the frequency domain; transforming the equaliser coefficients from the frequency domain to the time domain; and equalising the digital samples in the time domain using the transformed time domain equaliser coefficients.

Abstract: An apparatus and method for generating complementary periodic signals for a mixer circuit is provided. The apparatus comprises first and second generation circuits each for generating a periodic signal with a transition time on each rising edge different than a transition time on each falling edge. Each of the first and second generation circuits has an output for supplying its periodic signal to a mixer such that each rising edge of a periodic signal from one of the circuits crosses each falling edge of a periodic signal from the other of the circuits at a crossing point below a turn on voltage of the mixer.

Abstract: Circuitry and a method for use in a radio frequency receiver for processing a radio frequency signal are provided. The circuitry comprises a mixer arranged to receive the radio frequency signal and down-convert the received radio frequency signal to a lower frequency. The received radio frequency signal has an interference component and the interference component in the down-converted signal is within an interference frequency range. The circuitry also comprises an LC based notch filter arranged to receive the down-converted signal from the mixer, filter the down-converted signal, and output the filtered signal for processing by a baseband processing block. The LC based notch filter has a notch centered within said interference frequency range, such that the LC based notch filter is arranged to attenuate the interference component in the down-converted signal.

Abstract: A power supply noise rejection circuit for functional circuits, such as a voltage controlled oscillator (VCO). The power supply noise rejection circuit includes an isolation transistor connected to a voltage supply for providing an output current and voltage substantially free of noise across the full frequency range. A current source, a diode connected reference transistor with resistance means connected between its gate and drain terminals, and a dummy circuit serially connected between the voltage supply and ground generate a bias voltage that is applied to the gate of the isolation transistor. The dummy circuit mimics the DC characteristics of the functional circuit such that the output current tracks with process and temperature variations. The isolation transistor and the reference transistor can have negative threshold voltages, and the circuit can include bleed means for drawing current from the gate of the reference transistor and isolation transistor.

Abstract: A driver circuit for supplying a drive signal to a mixer circuit comprising a first and second circuit branch and an operational amplifier. The first circuit branch receives an input signal and a bias signal. The second circuit branch receives the input signal. The operational amplifier has a first input connected to a junction node of the first circuit branch and a second input connected to a junction node of the second circuit branch. The operational amplifier is arranged to provide an operational amplifier output signal a second component of the second circuit branch so that a voltage at the junction node of the second circuit branch is equal to a voltage at the junction node of the first circuit branch. The voltage is dependent on the input signal and providing the drive signal.

Abstract: Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value.

Abstract: A method, chip and computer program product for booting from a secondary boot source. In one embodiment, the method includes: (1) retrieving primary boot code from an on-chip primary boot source on the same chip as a processor, the primary boot code comprising at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, (2) executing the primary boot code on the processor, including the boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source, (3) retrieving the secondary boot code from the determined location and (4) continuing the booting of the processor by executing the secondary boot code on the processor.

Abstract: The disclosure provides a module for use in a wireless electronic device and being removable therefrom. In one embodiment, the module includes an antenna connector for connecting the antenna of the wireless terminal to the module, and transferring radio frequency signals over a wireless interface. The module also includes a first storage means storing user authentication information for use in authenticating a user of the wireless terminal to a wireless cellular network, and a second storage means storing communications code for processing information to be transferred over the wireless interface. The module further includes a processor arranged to execute the communications code in order to process information for communicating between the wireless terminal and the cellular network via the antenna connector.

Abstract: A method of accessing data in a device comprising: a first integrated circuit having a processor, a memory connected to the processor and a direct memory access engine operatively coupled to the memory and to the microprocessor; a second integrated circuit comprising storage means for holding data values in respective locations, the second integrated circuit being connected to the first integrated circuit via a serial link, the method comprising: the processor generating a plurality of memory access requests independent from one another and supplying a bundle of said independent memory access requests to the direct memory access engine, each memory access request comprising an address of a storage location in the storage means; the direct memory access engine sequentially supplying the memory access requests via the serial link to the second integrated circuit; the second integrated circuit returning a data value responsive to each memory access request and appending to the data value said address of the loca

Abstract: A method, program and user equipment for wireless communication in a cellular communication system comprising a plurality of base stations. The method comprises: synchronizing to one of said the base stations using a synchronization channel transmitted from that base station; receiving a pilot channel from said base station; after synchronizing to said base station, receiving a signal from that base station; and using the pilot channel from said base station to cancel interference on said signal caused by the synchronization channel.

Abstract: A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

Abstract: A method, program and apparatus for transmitting a signal in a time slot of a channel comprising a plurality of time slots. Using a transmitter having a processor and a power amplifier, the method comprises: retrieving a reference ramp pattern from a memory; determining an output power level for the slot from a plurality of possible output power levels, each requiring a respective corresponding ramp pattern; executing software on the processor to apply a scaling function to the reference ramp pattern in dependence on the determined output power level, thus generating a scaled ramp pattern corresponding to the pattern required for that determined level; supplying the scaled ramp pattern to a control input of the power amplifier, to control the gain of the power amplifier during the time slot; and using the power amplifier, controlled according to the scaled ramp pattern, to transmit the signal in the time slot.

Abstract: Systems are described that reduce or obviate the impact of limited processing resources and/or limit the power consumption in a receiver having signal processing functions at least partially implemented in software. A wireless receiver includes reception means for receiving a signal over a wireless channel in a wireless external environment. The receiver includes storage means, and a processor configured to perform a plurality of signal processing functions for extracting processed data from said signal, each of said signal processing functions having a plurality of alternative software implementations requiring different levels of usage of a processing resource. The processor estimates at least one parameter relating to the external environment and selects and executes one of the software alternatives for each of the respective signal processing functions to apply a set of implementations adapted to a required quality of said processed data. Related methods and computer program products are described.

Abstract: A method, apparatus and program. The method comprises: receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states; for each symbol in the sequence, determining a set of state metrics each representing a probability that the respective symbol corresponds to each of the plurality of states; and decoding the signal by processing runs of recursions, using runs of forward recursions and runs of reverse recursions. The decoding comprises performing a plurality of repeated iterations over the sequence, and for each iteration: dividing the sequence into a plurality of smaller windows, processing the windows using separate runs of recursions, and performing an associated warm-up run of recursions for each window.

Abstract: A method of transmitting data from a first module to addressable storage devices in a second module. The method comprises: transmitting from the first module to a second module in a first transmission cycle an address identifying a storage device in the second module for a data item; at the second module, determining the status of a storage location in the device identified by the address for holding a data item and dispatching in a second transmission cycle a pre-emptive acknowledgement signal, the state of which depends on the status of that storage location; transmitting in the second transmission cycle the data item from the first module to the second module; transmitting the address in a later transmission cycle from the first module to the second module; and selectively transmitting one of the data item and a next data item depending on the state of the pre-emptive acknowledgement signal.