Abstract: Methods of implementing fixed-point polynomials in hardware logic include distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial by solving an optimization problem that outputs an accuracy parameter and a precision parameter for each node. Each operator is then itself optimized to satisfy the part of the error bound allocated to that operator and as defined by the accuracy and precision parameters.

Abstract: Methods and systems for decoding an LDPC encoded data block using first and second sets of decoding parameters. The method includes iteratively decoding the LDPC encoded data block using a first set of decoding parameters. The decoding progress is monitored to determine whether the decoding has reached a non-progressing state. If it is determined that the decoding has reached a non-progressing state the decoding is terminated and iterative decoding of the LDPC encoded data block is restarted using a second set of decoding parameters. The second set of decoding parameters is different from the first set of decoding parameters.

Abstract: Methods and apparatus are provided for compressing and decompressing image data by producing two sets of reduced size image data, generating a modulation value for each elementary of the area from the image data, the modulation value encoding information about how to combine the sets of reduced size image data to generate an approximation to the image. In one arrangement, a set of index values is generated corresponding to a set of modulation values for each of the respective elementary areas of a group of elementary areas and these are assigned to each respective group and a second set of index values corresponding to one of the set of first index values for each elementary areas is assigned to each first group of elementary areas. These index values are stored for use in deriving modulation data more accurately when decompressing the image data.

Abstract: Ray tracing systems process rays through a 3D scene to determine intersections between rays and geometry in the scene, for rendering an image of the scene. Ray direction data for a ray can be compressed, e.g. into an octahedral vector format. The compressed ray direction data for a ray may be represented by two parameters (u,v) which indicate a point on the surface of an octahedron. In order to perform intersection testing on the ray, the ray direction data for the ray is unpacked to determine x, y and z components of a vector to a point on the surface of the octahedron. The unpacked ray direction vector is an unnormalized ray direction vector. Rather than normalizing the ray direction vector, the intersection testing is performed on the unnormalized ray direction vector. This avoids the processing steps involved in normalizing the ray direction vector.

Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h-1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.

Abstract: Methods and architectures for coordinating the operation of a plurality of processing units in a parallel computing architecture wherein each processing unit is configured to process work elements of dynamically generated work groups using a resource (e.g. memory) associated with the work group. The method includes requesting a resource (associated with one of the work groups) from a main storage for use by a first processing unit which causes the resource to be stored in a temporary storage (e.g.

Abstract: A logging unit is used to log entries for events in a computer system. Each entry includes an n-bit timestamp field and a payload. The payload includes information about the event and the timestamp field includes the n least significant bits of an N-bit timestamp for the event, where N>n. If the n least significant bits of the timestamp have wrapped compared to the corresponding n bits of the timestamp of the preceding entry then a timing entry is logged which includes other bits of the timestamp. Therefore, an N-bit timestamp can be determined for an event, but only the n least significant bits of the timestamp are stored in the timestamp field of an entry for the event. Therefore, the time flow of events in the store is better maintained (by having a larger timestamp) without increasing the number of bits (n) in the timestamp field of each entry.

Abstract: Embodiments disclosed pertain to apparatuses, systems, and methods for performing multi-precision single instruction multiple data (SIMD) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiply-add, rounding, saturation, and dot products on the above operand types. In addition, the circuit may facilitate 64-bit multiplication when Newton-Raphson, divide and square root operations are performed.

Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.

Abstract: A graphics processing unit is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises one or more processing cores configured to process graphics data. The graphics processing unit also comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles. The graphics processing unit also comprises scheduling logic configured to schedule, in dependence upon the cost indications, the sets of one or more tiles for processing on the one or more processing cores.

Abstract: A pixel filter receives a sequence of pixels, each pixel having an associated pixel value. A first recursive filter operation is performed in a first direction through the sequence of pixels to form a first filtered pixel value for each pixel, and a second recursive filter operation is performed in a second direction through the sequence of pixels to form a second filtered pixel value for each pixel. The first and second filtered pixel values for a given pixel are determined in dependence on the pixel value at that pixel and the filtered pixel value preceding that pixel in their respective direction of operation, the filtered pixel value of the preceding pixel being scaled by a measure of similarity between data associated with that pixel and its preceding pixel. For each pixel of the sequence, the first and second filtered pixel values are combined to generate a filter output for the pixel.

Abstract: When untransformed display lists are used in a tile-based graphics processing system, the processing involved in deriving sub-primitives may need to be performed in both the geometry processing phase and the rasterization phase. To reduce the duplication of this processing, the control stream data for a tile includes sub-primitive indications to indicate which sub-primitives are to be used for rendering a tile. This allows the sub-primitives to be determined efficiently in the rasterization phase based on this information determined in the geometry processing phase. Furthermore, a hierarchical cache system may be used to store a hierarchy of graphics data items used for deriving sub-primitives. If graphics data items for deriving a sub-primitive are stored in the cache, the retrieval of these graphics data items from the cache in the rasterization phase can reduce the amount of processing performed to derive the sub-primitives.

Abstract: An echo path monitoring system for controlling an adaptive filter configured to estimate an echo of a far-end signal comprised in a microphone signal, the system comprising a comparison generator configured to compare the microphone signal with the estimated echo to obtain a first comparison and compare an error signal, which represents a difference between the microphone signal and the estimated echo, with the estimated echo to obtain a second comparison, and a controller configured to combine the first and second comparisons to form a parameter indicative of a state of the microphone signal and, in dependence on said parameter, control an operating mode of the adaptive filter.

Abstract: A method of estimating the proximity of a first device to a second device in a network causes the first device to perform a first measurement in a first period during which a control message broadcasted over the network instructs devices in the network to not transmit during the first period, wherein the second device disregards the control message and transmits a first signal during the first period which is measured by the first device during the first period, and forms a measure of the proximity of the first device to the second device in dependence on a strength of the first signal.

Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. A bounding box is determined for the primitive. For each tile boundary between lines of tiles in the bounding box, intersection points of the tile boundary with edges of the primitive are determined and used to determine which of the tiles in the bounding box the primitive is in. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.

Abstract: Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.

Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: A gain control system for applying gain to a far-end signal, the system comprising: a signal identifier configured to detect an echo of the far-end signal in a microphone signal; and a path estimator configured to estimate a characteristic of an echo path of the detected echo, wherein: the signal identifier is further configured to detect a near-end signal from the microphone signal; and in response to detecting the near-end signal, the gain control system is configured to adjust the gain applied to the far-end signal in dependence on the estimated characteristic of the echo path.