Patents Assigned to Imagination Technologies
  • Patent number: 10474730
    Abstract: Median values for a stream of received data values in a data processing system (e.g. an image processing system) are determined. A first median value of the received data values within a first subset of data values of the received stream is determined, and intermediate data used for determining the first median value is stored. The stored intermediate data is used to determine a median value of the received data values within a second subset of data values of the received stream, wherein the second subset at least partially overlaps with the first subset. The determined median values are outputted for use in the data processing system, e.g. for further processing.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 12, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Timothy Lee
  • Patent number: 10475228
    Abstract: A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. The graphics processing system also comprises a cache system for storing graphics data for primitive fragments, the cache system including multiple cache subsystems. Each of the cache subsystems is coupled to a respective set of one or more processing engines. The graphics processing system also comprises a tile allocation unit which operates in one or more allocation modes to allocate tiles to processing engines. The allocation mode(s) include a spatial allocation mode in which groups of spatially adjacent tiles are allocated to the processing engines according to a spatial allocation scheme, which ensures that each of the groups of spatially adjacent tiles is allocated to a set of processing engines which are coupled to the same cache subsystem.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: November 12, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Jonathan Redshaw, Yoong Chert Foo
  • Patent number: 10460058
    Abstract: A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of ? input exponents, wherein ? is an integer that is a multiple of the reciprocal of the exponent of the power function; and for each recurrent input range of the hardware design, exhaustively simulating the hardware design over a simulation range to verify the property is true over the simulation range, wherein the simulation range comprises only ? input exponents.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 29, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Sam Elliott
  • Patent number: 10460507
    Abstract: During tracing of a primary ray in a 3-D space (e.g., a 3-D scene in graphics rendering), a ray is found to intersect a primitive (e.g., a triangle) located in the 3-D space. Secondary ray(s) may be generated for a variety of purposes. For example, occlusion rays may be generated to test occlusion of a point of intersection between the primary ray and primitive is illuminated by any of the light(s). An origin for each secondary ray can be modified from the intersection point based on characteristics of the primitive intersected. For example, an offset from the intersection point can be calculated using barycentric coordinates of the intersection point and interpolation of one or more parameters associated with vertices defining the primitive. These parameters may include a size of the primitive and differences between a geometric normal for the primitive and a respective additional vector supplied with each vertex.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: October 29, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Aaron Dwyer
  • Patent number: 10453164
    Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: October 22, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Steven J. Fishwick, John W. Howson
  • Patent number: 10453250
    Abstract: A graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles, includes geometry processing logic having geometry transform and sub-primitive logic configured to receive graphics data of input graphics data items, and to determine transformed positions within the rendering space of one or more sub-primitives derived from the input graphics data items using a plurality of shader stages; and a tiling unit configured to generate control stream data including sub-primitive indications to indicate which of the sub-primitives are to be used for rendering each tile. The geometry processing logic is configured to write to a memory, for each instance of a pre-determined shader stage, shader stage output data comprising data output from each instance of the pre-determined shader stage used to process the received graphics data.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: October 22, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson
  • Patent number: 10453245
    Abstract: Rendering system combines point sampling and volume sampling operations to produce rendering outputs. For example, to determine color information for a surface location in a 3-D scene, one or more point sampling operations are conducted in a volume around the surface location, and one or more sampling operations of volumetric light transport data are performed farther from the surface location. A transition zone between point sampling and volume sampling can be provided, in which both point and volume sampling operations are conducted. Data obtained from point and volume sampling operations can be blended in determining color information for the surface location. For example, point samples are obtained by tracing a ray for each point sample, to identify an intersection between another surface and the ray, to be shaded, and volume samples are obtained from a nested 3-D grids of volume elements expressing light transport data at different levels of granularity.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: October 22, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Cuneyt Ozdas, Luke Tilman Peterson
  • Patent number: 10438397
    Abstract: Ray tracing units, processing modules and methods are described for generating one or more reduced acceleration structures to be used for intersection testing in a ray tracing system for processing a 3D scene. Nodes of the reduced acceleration structure(s) are determined, wherein a reduced acceleration structure represents a subset of the 3D scene. The reduced acceleration structure(s) are stored for use in intersection testing. Since the reduced acceleration structures represent a subset of the scene (rather than the whole scene) the memory usage for storing the acceleration structure is reduced, and the latency in the traversal of the acceleration structure is reduced.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: October 8, 2019
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Luke T. Peterson
  • Patent number: 10437726
    Abstract: Cache logic for generating a cache address from a binary memory address comprising a first binary sequence of a first predefined length and a second binary sequence of a second predefined length, the cache logic comprising: a plurality of substitution units each configured to receive a respective allocation of bits of the first binary sequence and to replace its allocated bits with a corresponding substitute bit string selected in dependence on the received allocation of bits; a mapping unit configured to combine the substitute bit strings output by the substitution units so as to form one or more binary strings of the second predefined length; and combination logic arranged to combine the one or more binary strings with the second binary sequence by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10440255
    Abstract: Apparatus for controlling the focus of a camera arranged to capture a sequence of frames, includes an image processor configured to: form an image characteristic for a plurality of blocks of a first frame, each block comprising one or more pixels of the first frame; and calculate an image parameter for each block by combining the image characteristics of blocks lying within a predefined zone relative to that block; and a focus controller configured to derive a measure of focus for a selected frame area of the first frame by identifying a set of blocks whose respective predefined zones, when combined, substantially represent the selected frame area, and forming a measure of focus for the selected frame area by so combining the image parameters of the set of blocks; wherein the focus controller is configured to generate a signal for controlling camera focus in dependence on the measure of focus formed for the selected frame area of the first frame.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 8, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Paul Buxton
  • Patent number: 10424114
    Abstract: A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For each polygon, a determination is made whether that polygon is located at least partially inside a selected one of the smaller rectangular areas in the selected rectangular area. If so, which pixels of the plurality of pixels in the selected smaller rectangular area are inside the polygon are identified. Or, if that polygon is not located at least partially inside the selected smaller rectangular area, no further processing of the polygon is performed at one or more of the plurality of pixels in the smaller rectangular area.
    Type: Grant
    Filed: January 19, 2019
    Date of Patent: September 24, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Piers Barber, Simon Fenney
  • Patent number: 10425655
    Abstract: A compressed motion compensated video sequence is decoded using reference pictures (R) and motion vectors for deriving intermediate pictures (I,B) from reference pictures. The maximum vertical extent of the motion vector corresponds to a number of lines in the image data. A picture derived from the reference picture and motion vectors is decoded once the vertical extent of the reference picture received exceeds the maximum vertical extent of a motion vector from a starting position. Further set(s) of motion vectors for deriving further picture(s) can be received and for each picture to be derived, the image data is decoded using a respective further set of motion vectors after an area of a respective reference picture has been decoded to a maximum vertical extent of a motion vector from a starting position.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: September 24, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Krzysztof Bartczak
  • Patent number: 10417807
    Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3D scene. A hierarchical acceleration structure may be traversed by: traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 17, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Gregory Clark, John W. Howson, Justin DeCell, Steven J. Clohset
  • Patent number: 10419198
    Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: September 17, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Paul Rowland
  • Patent number: 10410408
    Abstract: Graphics processing systems can include lighting effects when rendering images. “Light probes” are directional representations of lighting at particular probe positions in the space of a scene which is being rendered. Light probes can be determined iteratively, which can allow them to be determined dynamically, in real-time over a sequence of frames. Once the light probes have been determined for a frame then the lighting at a pixel can be determined based on the lighting at the nearby light probe positions. Pixels can then be shaded based on the lighting determined for the pixel positions.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 10, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Jens Fursund, Luke T. Peterson
  • Patent number: 10409556
    Abstract: A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2n±1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2n±1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 10, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Thomas Rose
  • Patent number: 10402935
    Abstract: A method of profiling the performance of a graphics unit when rendering a scene according to a graphics pipeline, includes executing stages of the graphics pipeline using one or more units of rendering circuitry to perform at least one rendering task that defines a portion of the work required to render the scene, the at least one rendering task associated with a set flag; propagating an indication of the flag through stages of the graphics pipeline as the scene is rendered so that work done as part of the at least one rendering task is associated with the set flag; changing the value of a counter associated with a unit of rendering circuitry in response to an occurrence of an event while that unit performs an item of work associated with the set flag; and reading the value of the counter to thereby measure the occurrences of the event caused by completing the at least one rendering task.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 3, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Yoong-Chert Foo
  • Patent number: 10403004
    Abstract: Data compression (and corresponding decompression) is used to compress blocks of data values involving processes including one or more of color decorrelation, spatial decorrelation, entropy encoding and packing. The entropy encoding generates encoded data values which have variable sizes (in terms of the number of bits). The entropy encoding uses size indications for respective sets of data values to indicate the number of bits used for the encoded data values of the set. The size indications allow the encoded data values to be parsed quickly (e.g. in parallel).
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: September 3, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10402167
    Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h?1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 3, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Tim Lee
  • Patent number: 10395336
    Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 27, 2019
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick