Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.

Abstract: A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display. The memory includes at least one portion allocated to each rectangular area and at least one portion allocated as a global list.

Abstract: Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

Abstract: A data processing system includes a processor operable to execute a program partitioned into a number of discrete instructions, the processor having multiple processing elements each capable of executing more than one instruction per cycle, and an interface configured to read a first program and, on detecting a branch operation by that program creating m number of branches each having a different sequence of instructions, combine an instruction from one of the branches with an instruction from at least one of the other branches so as to cause a processing element to execute the combined instructions during a single cycle.

Abstract: Graphics processing systems and methods provide soft shadowing effects into rendered images. This is achieved in a simple manner which can be implemented in real-time without incurring high processing costs so it is suitable for implementation in low-cost devices. Rays are cast from positions on visible surfaces corresponding to pixel positions towards the center of a light, and occlusions of the rays are determined. The results of these determinations are used to apply soft shadows to the rendered pixel values.

Abstract: Graphics processing systems and methods provide soft shadowing effects into rendered images. This is achieved in a simple manner which can be implemented in real-time without incurring high processing costs so it is suitable for implementation in low-cost devices. Rays are cast from positions on visible surfaces corresponding to pixel positions towards the center of a light, and occlusions of the rays are determined. The results of these determinations are used to apply soft shadows to the rendered pixel values.

Abstract: Hardware logic is described which is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.

Abstract: A technique for efficient calling of functions on a processor generates an executable program having a function call by analysing an interface for the function that defines an argument expression and an internal value used solely within the function, and an argument declaration defining an argument value to be provided to the function when the program is run. A data structure is generated including the internal value and a resolved argument value derived from the argument expression and the argument value. A single instruction is encoded in the program to utilise the data structure. When the program is executed on a processor, the single instruction causes the processor to load the argument value and internal value from the data structure into registers in the processor, prior to evaluating the function. The function can then be executed without further register loads being performed.

Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.

Abstract: A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel.

Abstract: A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitive fragments, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will be subsequently hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.

Abstract: A method of scheduling tasks within a GPU or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. Wakeup event bits for task types, or combinations of task types and data groups, are set in response to completion of a task dependency and these wakeup event bits are used to select an oldest task from the queue that satisfies predefined criteria.

Abstract: Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q, r in response to any input pair N, D in a subset of non-negative input pairs.

Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.

Abstract: A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.

Abstract: A graphics processing system comprising: a tiling unit configured to tile a first view of a scene into a plurality of tiles; a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view; and a rendering unit configured to render to a render target each of the identified tiles.

Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3-D scene. A hierarchical acceleration structure may be traversed by: traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3-D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.

Abstract: A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is configured for receiving and decoding a timestamp in a beacon frame transmitted repeatedly from the access point. This is used to control the output signal of a station physical layer clock (12) which is then used as a clock source for an application layer time synchronisation protocol. This application layer time synchronisation protocol can then be used in the station to control an operating system clock (8) for regulating playback of media.

Abstract: Method and apparatus are provided for synchronizing execution of a plurality of threads on a multi-threaded processor. A program executed by a thread can have a number of synchronization points corresponding to points where execution is to be synchronized with another thread. Execution of a thread is paused when it reaches a synchronization point until at least one other thread with which it is intended to be synchronized reaches a corresponding synchronization point. Execution is subsequently resumed. A control core maintains status data for threads and can cause a thread that is ready to run to use execution resources that were occupied by a thread that is waiting for a synchronization event.