Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

Abstract: A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device received the first message from the third device according to the second clock; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.

Abstract: Methods and apparatus for compressing image data are described along with corresponding methods and apparatus for decompressing the compressed image data. An encoder unit, which generates the compressed image data, comprises an input arranged to receive a first image and a second image, wherein the second image is twice the width and height of the first image, a prediction generator arranged to generate a prediction texture from the first image using an adaptive interpolator, a difference texture generator arranged to generate a difference texture from the prediction texture and the second image and in encoder unit arranged to encode the difference texture.

Abstract: A method of estimating processor load at a device for transmitting a media stream, the device comprising an encoder and a processor capable of executing instructions for the encoder, the method comprising: encoding a first media frame and a second media frame at the encoder; determining a first time period between a first timestamp associated with the first media frame and a second timestamp associated with the second media frame; determining a second time period between a first completion time representing completion of the encoding of the first media frame and a second completion time representing completion of the encoding of the second media frame; and forming a measure of processor load in dependence on a difference between the first and second time periods.

Abstract: Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.

Abstract: A method of processing exceptions in an exception-driven computing-based system that operates in either initialization mode or exception-driven mode. The method includes, upon detecting an exception has occurred, causing the processor to execute exception handling instructions. When the system is operating in initialization mode the exception handling instructions invoke a first exception handler that causes a main register set to be saved before processing the exception and restored after processing the exception, and when the system is operating in exception-driven mode the exception handling instructions invoke a second exception handler that does not cause the main register set to be saved and restored. In some examples, the exception handling instructions are initially configured to invoke the first exception handler and are dynamically updated when the system switches from initialization mode to exception-driven mode to invoke the second exception handler.

Abstract: A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.

Abstract: A gain control system for dynamically tuning an echo canceller, the echo canceller being configured to estimate an echo of a far-end signal and subtract that echo estimate from a microphone signal to output an echo cancelled signal, the gain control system comprising a monitoring unit configured to estimate an energy associated with an impulse response of an adaptive filter configured to generate the echo estimate from the far-end signal and a gain tuner configured to adjust an attenuation of at least one of the microphone signal and the far-end signal in dependence on the estimated energy.

Abstract: An accurate implementation of a polynomial using floating-point or other rounded arithmetic can be generated using a plurality of hardware logic components which each implement an input polynomial such that the zeros in the input polynomial can be determined correctly. The number of different hardware logic components that are used can be reduced by analyzing the set of input polynomials and from it generating a set of polynomial components, where each polynomial in the set of input polynomials which is not also in the set of polynomial components, can be generated from a single one of the polynomial components.

Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in an instantiation of the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Abstract: A high definition timing synchronization function is described. In an embodiment, a wireless station generates a time stamp at a higher resolution than can be broadcast within a standard time stamp field in a frame. The generated time stamp is divided into two parts: the first part being included within the time stamp field and the second part being included within a vendor specific field in the same frame. The frame is transmitted by the wireless station and received by other wireless stations in the wireless network. If the receiving wireless station has the capability, it decodes both the time stamp field and the vendor specific field and recreates the higher resolution time stamp. This higher resolution time stamp is then used to synchronize the receiving wireless station and the transmitting wireless station by resetting a clock or by storing time stamps and corresponding clock values.

Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.

Abstract: A bounce light map for a scene is determined for use in rendering the scene in a graphics processing system. Initial lighting indications representing lighting within the scene are determined. For a texel position of the bounce light map, the initial lighting indications are sampled using an importance sampling technique to identify positions within the scene. Sampling rays are traced between a position in the scene corresponding to the texel position of the bounce light map and the respective identified positions with the scene. A lighting value is determined for the texel position of the bounce light map using results of the tracing of the sampling rays. By using the importance sampling method described herein, the rays which are traced are more likely to be directed towards more important regions of the scene which contribute more to the lighting of a texel.

Abstract: A method of scheduling tasks within a GPU or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. Wakeup event bits for task types, or combinations of task types and data groups, are set in response to completion of a task dependency and these wakeup event bits are used to select an oldest task from the queue that satisfies predefined criteria.

Abstract: A motion estimation technique finds first and second candidate bi-directional motion vectors for a first region of an interpolated frame of video content by performing double ended vector motion estimation on the first region. One of these candidate bi-directional motion vectors is selected, and used to identify a remote region of the interpolated frame. This remote region is located at an off-set location from the first region, and is found based on an endpoint of the selected candidate bi-directional motion vector. A remote motion vector for the remote region of the interpolated frame is obtained, and one or more properties of this remote motion vector are used to bias a selection between the first and second candidate vectors.

Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.

Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.

Abstract: Apparatus for binning an input value into an array of bins, each bin representing a range of input values and the bins collectively representing a histogram of input values, the apparatus comprising: an input for receiving the input value; a memory for storing the array; and a binning controller configured to: derive a plurality of bin values from the input value according to a binning distribution located about the input value, the binning distribution spanning a range of input values and each bin value having a respective input value dependent on the position of the bin value in the binning distribution; and allocate the plurality of bin values to a plurality of bins in the array, each bin value being allocated to a bin selected according to the respective input value of the bin value.

Abstract: A system for generating comfort noise for a stream of frames carrying an audio signal includes frame characterizing logic configured to generate a set of filter parameters characterising the frequency content of a frame; an analysis filter adapted using the filter parameters and configured to filter the frame so as to generate residual samples; an analysis controller configured to cause the residual samples to be stored in a store responsive to receiving an indication that the frame does not comprise speech; and a synthesis controller operable to select stored residual samples from the store and cause a synthesis filter, inverse to the analysis filter and adapted using filter parameters generated by the frame characterizing logic for one or more frames not comprising speech, to filter the selected residual samples so as to generate a frame of comfort noise.

Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.