Patents Assigned to IMEC
  • Patent number: 10386878
    Abstract: A PV module is described with an array of PV cells whereby the module is reconfigurable, allowing different configurations to be applied after installation and during operation, i.e. at run-time. The run time configuration of the module has controllable devices. The main controllable devices are any of (individually or in combination): a) switches which determine the parallel/series connections of the cells as well as hybrid cases also. b) switches between the cells and local dc/dc converters and/or among the DC/DC converters; c) actively controlled bypass diodes placed in order to allow excess current to flow in the occurrence of a mismatch.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: August 20, 2019
    Assignee: IMEC VZW
    Inventors: Francky Catthoor, Maria-Iro Baka
  • Patent number: 10382042
    Abstract: An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 13, 2019
    Assignee: IMEC vzw
    Inventors: Roeland Vandebriel, Geert Van der Plas, Vladimir Cherman
  • Patent number: 10381651
    Abstract: An method for manufacturing a electronic device is provided having a current collector capable of a high specific charge collecting area and power, but is also achieved using a simple and fast technique and resulting in a robust design that may be flexed and can be manufactured in large scale processing. To this end the electronic device comprising an electronic circuit equipped with a current collector formed by a metal substrate having a face forming a high-aspect ratio structure of pillars having an interdistance larger than 600 nm. By forming the high-aspect structure in a metal substrate, new structures can be formed that are conformal to curvature of a macroform or that can be coiled or wound and have a robust design.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: August 13, 2019
    Assignees: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO, IMEC vzw
    Inventors: Sandeep Unnikrishnan, Philippe Vereecken
  • Patent number: 10376175
    Abstract: The disclosure relates to a sensor, a system, and a holder arrangement for biosignal activity measurement. One example embodiment includes a sensor module for brain activity measurement. The sensor module includes a main electrode base. The sensor module also includes a plurality of pins protruding from the main electrode base. The plurality of pins is arranged such that, when applied on a subject, the pins make contact with skin of the subject or are in close proximity with the skin of the subject. The main electrode base comprises electronic circuitry for near infrared spectroscopy (NIRS) measurements and electronic circuitry for electroencephalography (EEG) measurements, both connected to the plurality of pins. The plurality of pins includes electrically conductive pins. The plurality of pins also includes at least one source waveguide pin configured for light emitting purposes or at least one detector waveguide pin configured for light detection purposes.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: August 13, 2019
    Assignees: IMEC VZW, Stichting IMEC Nederland
    Inventors: Srinjoy Mitra, Bernard Grundlehner
  • Patent number: 10374218
    Abstract: A method is provided for forming a porous, electrochemically active lithium manganese oxide layer on a substrate, the method comprising: depositing a porous manganese oxide layer on the substrate; providing a Li containing layer on the porous manganese oxide layer; and afterwards performing an annealing step at a temperature in the range between 200° C. and 400° C., thereby inducing a solid-state reaction between the porous manganese oxide layer and the Li containing layer. The method may further comprise, before depositing the porous manganese oxide layer: depositing a seed layer on the substrate. A method of the present disclosure may be used for forming electrode layers of lithium-ion batteries.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 6, 2019
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Nouha Labyedh, Marina Yurievna Timmermans, Philippe Vereecken
  • Patent number: 10372868
    Abstract: The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 6, 2019
    Assignee: IMEC VZW
    Inventors: Yanxiang Huang, Chunshu Li, Meng Li
  • Patent number: 10369775
    Abstract: The disclosed technology generally relates to preparing two-dimensional material layers, and more particularly to releasing a graphene layer from a template substrate. According to an aspect, a method of releasing a graphene layer includes providing a template substrate on which the graphene layer is provided, the method comprising: subjecting the graphene layer and the template substrate to a water treatment by soaking the graphene layer and the template substrate in water such that water is intercalated between the template substrate and the graphene layer; and subjecting the graphene layer and the template substrate to a delamination process, thereby releasing the graphene layer from the template substrate.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: August 6, 2019
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Steven Brems, Cedric Huyghebaert, Ken Verguts, Stefan De Gendt
  • Patent number: 10374084
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to vertical channel devices and a method of making the same. In one aspect, a method of forming vertical channel devices includes forming a first vertical channel structure extending from a first bottom electrode region and a second vertical channel structure extending from a second bottom electrode region. The first and the second vertical channel structures protrude from a dielectric layer covering the first and second bottom electrode regions. The method additionally comprises forming a first hole exposing the first bottom electrode region and a second hole exposing the second bottom electrode region, where the first and the second holes extending vertically through the dielectric layer. The method additionally includes forming a conductive pattern including a set of discrete pattern parts on the dielectric layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 6, 2019
    Assignee: IMEC vzw
    Inventor: Juergen Boemmels
  • Patent number: 10367031
    Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 30, 2019
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Anne Vandooren, Nadine Collaert
  • Publication number: 20190229196
    Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second se
    Type: Application
    Filed: January 22, 2019
    Publication date: July 25, 2019
    Applicants: IMEC VZW, GLOBALFOUNDRIES INC.
    Inventors: Syed Muhammad Yasser Sherazi, Julien Ryckaert, Juergen Boemmels, Guillaume Bouche
  • Patent number: 10359694
    Abstract: The disclosure is related to a lithographic mask for EUV lithography, to a method for producing the mask, to a method for printing a pattern with the mask, to a stepper/scanner configured to print a pattern with the mask as well as to a computer-implemented method for calculating a deformation of the pattern. The mask comprises an absorber pattern, which is intentionally deformed in the 2-dimensional plane of the EUV mask, with respect to the intended pattern. The deformation of the pattern is based on a previous measurement of the location of multilayer defects on the blank, and calculated so that in the deformed pattern, a maximum of multilayer defects are covered by absorber material. When the pattern is subsequently printed on a semiconductor wafer in a stepper/scanner, the scanner operation is modulated so that the pattern deformation is not reproduced on the wafer.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 23, 2019
    Assignee: IMEC VZW
    Inventors: Rik Jonckheere, Koen D'have
  • Patent number: 10359363
    Abstract: A sensor device for quantifying luminescent targets. The device comprises a light source for exciting the targets, thus generating luminescence signals, and a detector for detecting these signals of the targets in a cell, resulting in a detected signal comprising a desired signal and a background signal. The detector has a spatial cell resolution and/or a time resolution that is so high that only a limited number of targets will be present in the cell when measuring at low concentration and/or that only a limited number of targets add to the cell in between two measurements. A change in the number of targets in the cell can be observed in the detected signal. The device comprises a processor configured to distinguish the desired and the background signal, and to combine the detected signals of the different cells and/or moments in time, to quantify the targets.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: July 23, 2019
    Assignee: IMEC VZW
    Inventors: Peter Peumans, Liesbet Lagae, Willem Van Roy, Tim Stakenborg, Pol Van Dorpe
  • Patent number: 10361268
    Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: July 23, 2019
    Assignee: IMEC VZW
    Inventors: Kurt Wostyn, Hans Mertens, Liesbeth Witters, Andriy Hikavyy, Naoto Horiguchi
  • Patent number: 10353284
    Abstract: The present disclosure provides a lithographic reticle system comprising a reticle, a first pellicle membrane mounted in front of the reticle, and a second pellicle membrane mounted in front of the first pellicle membrane, wherein the first pellicle membrane is arranged between the reticle and the second pellicle membrane, and wherein the second pellicle membrane is releasably mounted in relation to the first pellicle membrane and the reticle.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 16, 2019
    Assignees: IMEC VZW, IMEC USA NANOELECTRONICS DESIGN CENTER
    Inventors: Rik Jonckheere, Cedric Huyghebaert, Emily Gallagher
  • Patent number: 10355128
    Abstract: A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: July 16, 2019
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Praveen Raghavan, Odysseas Zografos
  • Patent number: 10354868
    Abstract: A method for formation of a transition metal dichalcogenide (TMDC) material layer on a substrate arranged in a process chamber of a molecular beam epitaxy tool is provided. The method includes evaporating metal from a solid metal source, forming a chalcogen-including gas-plasma, and introducing the evaporated metal and the chalcogen-including gas-plasma into the process chamber thereby forming a TMDC material layer on the substrate.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 16, 2019
    Assignee: IMEC VZW
    Inventors: Salim El Kazzi, Clement Merckling
  • Publication number: 20190213947
    Abstract: A conformable matrix display device is provided with row conductors on the conformable carrier, each for a respective row of the matrix of pixel circuits. Each row conductor has serpentine trajectories in spaces between the pixel circuits in the respective row. Power supply voltage and selection pulse signals are transmitted over the same row conductors. Each row conductor is connected to supply voltage and selection inputs of the pixel circuits in the respective row. Each pixel circuit has a pulse transmission circuit coupled etween the selection input and the control input of a de-multiplexing circuit for de-multiplexing data signals on column conductors. In this way the power supply voltage and the selection signal can be supplied making shared use of space between the pixel circuits. Thus the number of conductors in the matrix display device is reduced, which enables a greater distance between the conductors and/or bends in the conductors, which makes the circuit more stretchable and/or bendable.
    Type: Application
    Filed: May 26, 2017
    Publication date: July 11, 2019
    Applicants: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO, IMEC vzw
    Inventors: Brian Hardy COBB, Jan GENOE
  • Patent number: 10347536
    Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: July 9, 2019
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Nadine Collaert
  • Patent number: 10340139
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 2, 2019
    Assignee: IMEC
    Inventors: Benjamin Vincent, Voon Yew Thean, Liesbeth Witters
  • Patent number: 10338313
    Abstract: An on-chip broadband radiation source, and methods for its manufacture such that a photonics IC comprises an optical waveguide such as a semiconductor waveguide, a thin III-V material membrane with absorption capability for absorbing an optical pump signal induced in the waveguide. The III-V membrane comprises a LED implemented therein. The photonics IC also comprises a coupling means between the waveguide and the membrane. The device provides a broadband radiation source at a wavelength longer than the wavelength of the transferred radiation. The broadband signal can then be coupled out through the waveguide and used in the chip.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: July 2, 2019
    Assignees: UNIVERSITEIT GENT, IMEC VZW
    Inventors: Roeland Baets, Günther Roelkens, Andreas De Groote, Paolo Cardile, Ananth Subramanian