Patents Assigned to IMEC
  • Publication number: 20200335482
    Abstract: An LED array mounted on a circuit board including a plurality of LED chips embedded in an encapsulant. Each LED chip is placed inside a cavity which is made up solely from a multilayer foil and attached to the circuit board with an adhesive film. The foil cavity design enables a variety of mounted LED arrays to be manufactured with the same process.
    Type: Application
    Filed: November 12, 2018
    Publication date: October 22, 2020
    Applicants: BARCO N.V., IMEC VZW, UNIVERSITEIT GENT
    Inventors: Saso MLADENOVSKI, Jasper Irene LAMBERT, Stephanie Cyriel Adrianna VAN HAECKE, Floris Albert BONTINCK, Jindrich WINDELS, Michal JABLONSKI
  • Patent number: 10811315
    Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: IMEC vzw
    Inventors: Gaspard Hiblot, Stefaan Van Huylenbroeck, Geert Van der Plas
  • Patent number: 10811542
    Abstract: A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 20, 2020
    Assignee: IMEC VZW
    Inventor: Carolina Mora Lopez
  • Patent number: 10802743
    Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 13, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Francky Catthoor, Praveen Raghavan, Daniele Garbin, Dimitrios Rodopoulos, Odysseas Zografos
  • Patent number: 10797224
    Abstract: The disclosed technology generally relates to magnetoresistive devices, and more particularly to a magnetic tunnel junction (MTJ) device formed in an interconnection structure, and to a method of integrating the (MTJ) device in the interconnection structure. According to an aspect, a device includes a first interconnection level including a first dielectric layer and a first set of conductive paths arranged in the first dielectric layer, a second interconnection level arranged on the first connection level and including a second dielectric layer and a second set of conductive paths arranged in the second dielectric layer, and a third interconnection level arranged on the second interconnection level and including a third dielectric layer and a third set of conductive paths arranged in the third dielectric layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 6, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Praveen Raghavan, Davide Francesco Crotti, Raf Appeltans
  • Patent number: 10797016
    Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 6, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Vikas Dubey, Eric Beyne, Giovanni Capuz
  • Patent number: 10790382
    Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 29, 2020
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Silvia Armini, Elisabeth Camerotto, Zheng Tao
  • Patent number: 10782607
    Abstract: An example method for making a reticle includes providing an assembly. The assembly includes an extreme ultraviolet mirror and a cavity overlaying at least a bottom part of the extreme ultraviolet mirror. The method also includes at least partially filling the cavity with an extreme ultraviolet absorbing structure that includes a metallic material that includes an element selected from Ni, Co, Sb, Ag, In, and Sn, by forming the extreme ultraviolet absorbing structure selectively in the cavity.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 22, 2020
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Boon Teik Chan, Kim Vu Luong, Vicky Philipsen, Efrain Altamirano Sanchez, Kevin Vandersmissen
  • Patent number: 10784158
    Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 22, 2020
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Efrain Altamirano Sanchez
  • Patent number: 10777471
    Abstract: The disclosed technology generally relates to semiconductor characterization, and more particularly to detecting manufacturing defects in semiconductor regions. In one aspect, a non-destructive method of detecting a manufacturing defect in a semiconductor device includes providing a semiconductor device comprising an electrically isolated conductive via formed in a semiconductor region. The method additionally includes locally heating to cause a temperature change in a volume of the semiconductor region from a first temperature to a second temperature. The method additionally includes applying an electrical bias between the conductive via and the semiconductor region to form a temperature-dependent depletion region in the semiconductor region.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 15, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Kristof J. P. Jacobs, Ingrid De Wolf
  • Patent number: 10778926
    Abstract: Example embodiments relate to an image sensor and a method for read-out of pixel signal. One embodiment includes an image sensor. The image sensor includes an array of pixels for detecting light incident on the pixel. The image sensor also includes an in-pixel correlated double sampling (CDS) circuitry. The image sensor also includes a column line that extends along and is associated with a column of pixels in the array of pixels. The column line is configured to selectively receive a pixel signal from a pixel in the column. Further, the image sensor includes a voltage-drop correction line that extends along and is associated with the column of pixels. The voltage-drop correction line is configured to provide a correction voltage signal to a pixel in the column such that corrects for voltage drop of the pixel signal in read-out through the column line.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 15, 2020
    Assignee: IMEC VZW
    Inventors: Annachiara Spagnolo, Jonathan Borremans
  • Patent number: 10778190
    Abstract: A device for phase shifting is disclosed, comprising an input amplifier, a biasing circuit, a first output amplifier and a second output amplifier being variable-gain amplifiers, and a quadrature hybrid coupler. The input amplifier is connected to an input port of the coupler, the first output amplifier is connected to a through port of the coupler, the second output amplifier is connected to a coupled port of the coupler, and the biasing circuit is connected to an isolated port of the coupler. The device also includes, the quadrature hybrid coupler configured to receive, at the input port, an input signal from the input amplifier, output, at the through port, a through signal, receive, at the isolated port, a bias signal from the biasing circuit, and output, at the coupled port, a coupled signal having a phase differing from a phase of the through signal.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 15, 2020
    Assignee: IMEC vzw
    Inventors: Kristof Vaesen, Pierre Wambacq
  • Patent number: 10775254
    Abstract: A force sensing device comprises: a membrane (120), which is configured to deform upon receiving a force; a first Mach Zehnder-type interferometer device (110); a second Mach Zehnder-type interferometer device (130), wherein a first measurement propagation path (114) of the first Mach Zehnder-type interferometer device (110) and a second measurement propagation path (134) of the second Mach Zehnder-type interferometer device (130) are arranged on or in the membrane (120), and wherein the first measurement propagation path (114) and the second measurement propagation path (134) are differently sensitive to applied force on the membrane (120).
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 15, 2020
    Assignee: IMEC VZW
    Inventors: Roelof Jansen, Xavier Rottenberg, Veronique Rochus
  • Patent number: 10770213
    Abstract: The disclosed technology generally relates to a magnetoresistive device and more particularly to a magnetoresistive device comprising chromium. According to an aspect, a method of forming a magnetoresistive device comprises forming a magnetic tunnel junction (MTJ) structure over a substrate. The MTJ structure includes, in a bottom-up direction away from the substrate, a free layer, a tunnel barrier layer and a reference layer. The method additionally includes forming a pinning layer over the MTJ structure, wherein the pinning layer pins a magnetization direction of the reference layer. The method additionally includes forming capping layer comprising chromium (Cr) over the pinning layer. The method further includes annealing the capping layer under a condition sufficient to cause diffusion of Cr from the capping layer into at least the pinning layer. According to another aspect, a magnetoresistive device is formed according to the method.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 8, 2020
    Assignee: IMEC vzw
    Inventors: Johan Swerts, Sebastien Couet
  • Patent number: 10770295
    Abstract: An example embodiment includes a patterning method comprising: forming a layer stack comprising a target layer, a lower memorization layer and an upper memorization layer, forming above the upper memorization layer a first mask layer, patterning a set of upper trenches in the upper memorization layer, forming a first block pattern, the first block pattern comprising a set of first blocks, patterning a first set of lower trenches in the lower memorization layer, patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, forming above the patterned lower memorization layer and the second block pattern a second mask layer, patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 8, 2020
    Assignee: IMEC VZW
    Inventors: Frederic Lazzarino, Victor M. Blanco
  • Patent number: 10767263
    Abstract: A method of producing a metal-organic framework (MOF) film on a substrate is provided. The method includes providing a substrate having a main surface and forming on the main surface a MOF film using an organometallic compound precursor and at least one organic ligand, wherein each of the organometallic compound precursor and the at least one organic ligand is provided only in the vapour phase.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 8, 2020
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D.
    Inventors: Ivo Stassen, Rob Ameloot, Dirk De Vos, Philippe M. Vereecken
  • Patent number: 10768138
    Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 8, 2020
    Assignee: IMEC VZW
    Inventors: Koen Martens, Nadine Collaert, Eddy Kunnen, Simone Severi
  • Patent number: 10763643
    Abstract: An electrically-operated semiconductor laser device and method for forming the laser device are provided. The laser device includes a fin structure to which a waveguide is optically coupled. The waveguide is optically coupled to passive waveguides at either end thereof. The fin structure includes an array of fin elements, each fin element comprising Group III-V materials.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 1, 2020
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R& D, Universiteit Gent
    Inventors: Joris Van Campenhout, Clement Merckling, Maria Ioanna Pantouvaki, Ashwyn Srinivasan, Irina Kulkova
  • Patent number: 10763159
    Abstract: A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 1, 2020
    Assignee: IMEC vzw
    Inventors: Basoene Briggs, Christopher Wilson, Juergen Boemmels
  • Patent number: 10749106
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices comprising a magnetic tunnel junction (MTJ). In an aspect, a method of forming a magnetoresistive random access memory (MRAM) includes forming a layer stack above a substrate, where the layer stack includes a ferromagnetic reference layer, a tunnel barrier layer and a ferromagnetic free layer and a spin-orbit-torque (SOT)-generating layer. The method additionally includes, subsequent to forming the layer stack, patterning the layer stack to form a MTJ pillar.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 18, 2020
    Assignee: IMEC vzw
    Inventors: Hanns Christoph Adelmann, Gouri Sankar Kar, Johan Swerts, Sebastien Couet