Abstract: A method of wireless ranging between an initiator node and a responder node, involves performing a measurement procedure resulting in a two-way phase measurement between an initiator node and a responder node, the measurement procedure involving the initiator node transmitting an initiator carrier signal; the responder node performing a phase measurement of the initiator carrier signal relative to a responder node clock reference; the responder node transmitting a responder carrier signal; and the initiator node performing a phase measurement of the responder carrier signal relative to the initiator node clock reference, the method further involving calculating a distance between the initiator node and the responder node using as input the two-way phase measurements for the plurality of nominal frequencies; and a clock reference offset correction of the initiator node and of the responder node.

Abstract: A polar transmitter is provided. The polar transmitter includes a baseband generation unit configured to generate phase data bits and amplitude data bits of an output pulse. The polar transmitter further includes a bandwidth control unit downstream to the baseband generation unit configured to regulate the width of the output pulse. Moreover, the polar transmitter includes a pulse shaping unit downstream to the bandwidth control unit configured to generate a predefined amplitude envelope of the output pulse. In this context, the pulse shaping unit includes a delay-line with a plurality of taps, where each tap output is configured to be amplitude weighted in order to generate the amplitude envelope of the output pulse.

Abstract: The present disclosure relates to a fluid analyzing device that includes a sensing device for analyzing a fluid sample. The sensing device includes a microchip configured for sensing the fluid sample, and a closed micro-fluidic component for propagating the fluid sample to the microchip. The fluid sample can be provided to the micro-fluidic component via an inlet of the fluid analyzing device. And a vacuum compartment, which is air-tight connected to the sensing device, can create in the micro-fluidic component a suction force suitable for propagating the fluid sample through the micro-fluidic component.

Abstract: A method for three-dimensional imaging of a sample (302) comprises: receiving (102) interference patterns (208) acquired using light-detecting elements (212), wherein each interference pattern (208) is formed by scattered light from the sample (302) and non-scattered light from a light source (206; 306), wherein the interference patterns (208) are acquired using different angles between the sample (302) and the light source (206; 306); performing digital holographic reconstruction applying an iterative algorithm to change a three-dimensional scattering potential of the sample (302) to improve a difference between the received interference patterns (208) and predicted interference patterns based on the three-dimensional scattering potential; wherein the iterative algorithm reduces a sum of a data fidelity term and a non-differentiable regularization term and wherein the iterative algorithm includes a forward-backward splitting method alternating between forward gradient descent (108) on the data fidelity term

Abstract: An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

Abstract: An electrode (10) for transcranial current stimulation is provided. The electrode (10) comprises at least two pins (11a, 11b) for contacting the skin of a living or human being, and a current delivering unit (12) connected to the at least two pins (11a, 11b). The current delivering unit (12) is configured to estimate the corresponding range of the respective contact impedance with respect to the skin for each of the at least two pins (11a, 11b) or to analyze the corresponding level of the respective contact impedance with respect to the skin for each of the at least two pins (11a, 11b). The current delivering unit (12) is configured to distribute a desired current over all of the at least two pins (11a, 11b) or to select a set of the at least two pins (11a, 11b) for delivering a set of partial currents in order to achieve the desired current.

Abstract: A photonics reservoir computing system is described. The system is configured for propagating at least one optical signal so as to create resulting radiation signals in the output channels. The photonics reservoir computing system further comprises weighting elements for weighting signals from the output channels, and at least one optical detector for optically detecting signals from the output channels. The system is adapted for estimating signals from the output channels through an output of the optical detector.

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising: forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks; the method further comprising, prior to said processing: by etching removing the sacrificial layer of each layer stack to form a respect

Abstract: According to an aspect of the present inventive concept there is provided a method for manufacturing a fluid sensor device comprising: bonding a silicon-on-insulator arrangement comprising a silicon wafer, a buried oxide, a silicon layer, and a first dielectric layer, to a CMOS arrangement comprising a metallization layer and a planarized dielectric layer, wherein the bonding is performed via the first dielectric layer and the planarized dielectric layer; forming a fin-FET arrangement in the silicon layer, wherein the fin-FET arrangement is configured to function as a fluid sensitive fin-FET arrangement; removing the buried oxide and the silicon wafer; forming a contact to the metallization layer and the fin-FET arrangement, wherein the contact comprises an interconnecting structure configured to interconnect the metallization layer and the fin-FET arrangement; forming a channel comprising an inlet and an outlet, wherein the channel is configured to allow a fluid comprising an analyte to contact the fin-FET a

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell

Abstract: A device for analysis of cells comprises: an integrated circuit arrangement on a substrate; a dielectric layer formed above the integrated circuit arrangement; a microelectrode array layer formed above the dielectric layer, said microelectrode array layer comprising a plurality of individual electrodes, wherein each electrode is connected to the integrated circuit arrangement through a via in the dielectric layer; and wherein a plurality of longitudinal trenches in the dielectric layer and the microelectrode array layer are for stimulating cell growth on a surface of the device

Abstract: A method for manufacturing an III-nitride semiconductor structure is provided.

Abstract: A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.

Abstract: The present disclosure provides an HBT that includes (i) a semiconductor support layer; at least four wall structures side-by-side on the support layer; (iii) a semiconductor collector-material ridge structure disposed on the support layer between two adjacent wall structures of the at least four wall structures; (iv) a semiconductor base-material layer, wherein a first part of the base-material layer is disposed on a first region of the ridge structure and a second part of the base-material layer is disposed across the wall structures, wherein the base-material layer is supported by the wall structures; (v) a semiconductor emitter-material layer disposed on the first part of the base-material layer; (vi) a base contact layer disposed on the second part of the base-material layer; an emitter contact layer disposed on the emitter-material layer; and (viii) a collector contact layer disposed on a second region of the ridge structure.

Abstract: A passive photonics reservoir computing system comprises an optical waveguide based structure comprising a plurality of discrete nodes and a plurality of passive waveguide interconnections between the nodes for propagating the at least one photonic signal between the nodes, in which each discrete node is adapted for passively relaying the at least one photonic wave over the passive waveguide interconnections connected thereto, wherein the optical waveguide based structure comprises at least one multimode Y-junction configured for connecting three waveguides using a taper section wherein the taper section is not perfectly adiabatic. A training scheme uses a passive photonics computing system.

Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.

Abstract: A photo-sensitive device comprises: an active layer configured to generate charges in response to incident light; a charge transport layer arranged below the active layer, wherein the charge transport layer comprises a first portion and a second portion being laterally displaced in relation to the first portion; a gate separated by a dielectric material from the charge transport layer, wherein said gate is arranged below the first portion and configured to control a potential thereof; and a transfer gate, which is separated by a dielectric material from a transfer portion of the charge transport layer between the first portion and the second portion, wherein the transfer gate is configured to control transfer of accumulated charges in the first portion to the second portion for read-out of detected light.

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

Abstract: An orthogonal frequency-division multiplexing (OFDM) based radar signal comprising Q sub-carriers adapted to push an IQ-imbalance component out of a subset of L contiguous range bins of range profiles derived out of the received radar signal and wherein L is at most Q/2, is disclosed.

Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.