Abstract: A method of forming an interconnect structure for a standard cell semiconductor device is disclosed. In one aspect, the method includes forming metal lines along respective routing tracks, wherein forming the metal lines includes depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer; patterning the capping layer and the metal layer to form first and second capped off-center metal lines extending along first and second off-center tracks, respectively; forming spacer lines on sidewalls of the capped off-center metal lines; and embedding the spacer-provided capped off-center metal lines in a second dielectric layer. The method further includes patterning a set of trenches in the second dielectric layer.

Abstract: The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device.

Abstract: An analog-to-digital converter, ADC, module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal, wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value; wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, receive the coarse digital value as an initial approximation of the analog signal and track the analog signal during a finite duration.

Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.

Abstract: A p-channel metal-oxide-semiconductor (pMOS) transistor including a gate stack which includes: a silicon oxide comprising dielectric interlayer on a substrate, wherein the dielectric interlayer has a thickness below 1 nm; a high-k dielectric layer having a higher dielectric constant compared to the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate, where the first dipole-forming capping layer has a thickness below 2 nm; at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and therefore high reliability without the use of a reliability anneal which makes the pMOS transistor suitable for use as back end of line (BEOL) devices.

Abstract: A method for writing data including a sequence of bits, the data being written in a form of DNA, by in-vitro enzymatically producing memory DNA from a strand of memory writing substrate DNA is disclosed. In one aspect, the method includes repeating of: receiving a sub-sequence of the sequence of bits, the sub-sequence including at least one bit; selecting memory nucleotides based on the sub-sequence; contacting, in liquid medium including the strand of memory writing substrate DNA contacted with an enzyme, the selected memory nucleotides and the enzyme; and synthesizing a portion of the memory DNA from a portion of the strand of memory writing substrate DNA by the enzyme and at least one of the memory nucleotides of the solution, thereby producing memory DNA including memory nucleotides corresponding to bits of the sequence of bits. The disclosed technology further relates to a micro-fluidic system including a microfluidic chip and a controller.

Abstract: A storage device including a tape configured to store data is disclosed. The tape includes a plurality of first regions with a first dielectric constant and a plurality of second regions with a second dielectric constant that is higher than the first dielectric constant. The first regions and the second regions are arranged in an alternating manner along the length of the tape. Further, the storage device includes one or more actuators configured to apply an electrical field across the width of the tape, in order to move the tape in length direction. Further, the storage device includes one or more data heads configured to read and/or write data from and/or to the tape.

Abstract: The present invention relates to a method for writing data comprising a sequence of bits, the data being written in a form of nucleic acid, by in-vitro enzymatically producing memory nucleic acid from a strand of memory writing substrate nucleic acid, wherein the strand of memory writing substrate nucleic acid comprises a plurality of spacer sections and memory writing sections sandwiched between the spacer sections. Each of the spacer sections comprises one or more nucleobases, and each of the memory writing sections comprises a nucleobase other than the nucleobases of an adjacent spacer section upstream of the memory writing section in a travel direction of an enzyme along the strand of memory writing substrate nucleic acid.

Abstract: A method for forming airgaps within an integrated electronic circuit implements a conformal layer and a nanosheet both of boron nitride. The method has advantages for the circuit due to special properties of boron nitride material. In particular, mechanical strength and heat dissipation are increased whereas electro-migration is limited. The method may be applied to the first interconnect layer of the integrated circuit, for reducing additionally capacitive interactions existing between gate electrode structures and source or drain contact structures.

Abstract: Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

Abstract: An apparatus is provided for on-chip reconstruction of transient settling behavior. The apparatus comprises a first sampling circuit configured to sample a tracked analog signal output from a circuit under test over an operating period at a first sampling time, thereby generating a first sample output. In addition, the apparatus comprises a second sampling circuit configured to sample the tracked analog signal output at a second sampling time, thereby generating a second sample output. The apparatus further comprises a signal subtraction circuit configured to perform subtraction of the first sample output and the second sample output, thereby generating a difference signal. Moreover, the apparatus comprises a signal conversion circuit configured to output the difference signal in the digital domain.

Abstract: A micro-fluidic device 100 for performing digital PCR is presented. The device comprises: a semiconductor substrate; a first micro-fluidic channel 104, comprising an inlet 102 and an outlet 103, embedded in the semiconductor substrate; a heating element 101 thermally coupled to the first micro-fluidic channel 104; a droplet generator 107 connected to the inlet 102 of the first micro-fluidic channel 104 for generating droplets and pumping generated droplets at a flow rate into the first micro-fluidic channel 104; characterized in that: the heating element 101 is a single heating element connected to a temperature control unit 111 configured to cycle the temperature of the complete first micro-fluidic channel 104 through at least two temperature values; and wherein the flow rate of the droplet generator 107 is adaptable. Further, a method to perform digital PCR is presented using the micro-fluidic device 100.

Abstract: Example embodiments relate to monolithically integrated antenna devices. One embodiment includes a monolithically integrated antenna device that includes a substrate having a first surface and a second surface. The monolithically integrated antenna device also includes a transistor component layer that includes at least one electronic component therein. Further, the monolithically integrated antenna device includes at least one antenna structure formed on the substrate or the transistor component layer. The antenna structure is configured to operate in a frequency range of between 30 kHz and 2.4 GHz. The substrate is configured to have a size that is the same or larger than the at least one antenna structure. The at least one antenna structure is formed in a stack with the transistor component layer and the substrate. The monolithically integrated antenna device is configured to shield the at least one electronic component in the transistor component layer from electromagnetic interference.

Abstract: A device for synthesis of macromolecules is disclosed. In one aspect, the device comprises an ion-releaser having a synthesis surface comprising an array of synthesis locations arranged for synthesis of the macromolecules. The ion-releaser also includes an ion-source electrode, which is arranged to contain releasable ions and is arranged to be in contact with each of the synthesis locations of the synthesis surface, thereby release ions to the synthesis locations. The ion-releaser further comprises activating electrodes, which are arranged to be in contact with the ion-source electrode, wherein each one of the activating electrodes is arranged in association with one of the synthesis locations via the ion-source electrode. The ion-releaser is arranged to release at least a portion of the releasable ions from the ion-source electrode to one of the synthesis locations, by activation of the activating electrode associated with the synthesis location.

Abstract: The present disclosure relates to a spectral sensor for detection of individual light-emitting particles. The sensor is comprising an array of photo-sensitive detectors for detecting light emitted by said individual light-emitting particles and a filter array comprising a plurality of different band-stop filters. The filter array is configured to transmit wavelengths in a detectable wavelength region to the array of photo-sensitive detectors, and wherein each band-stop filter is associated with one or more particular photo-sensitive detectors, and the plurality of different band-stop filters are configured to reflect different wavelength intervals within said detectable wavelength region so that each photo-sensitive detector of the array is configured to detect the wavelengths of the detectable wavelength region other than the reflected wavelength interval of the band-stop filter being associated with the photo-sensitive detector.

Abstract: A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions.

Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.

Abstract: The disclosed technology generally relates to semiconductor devices and methods of manufacturing semiconductor devices such as both logic and memory semiconductor devices. In one aspect, a semiconductor device includes a semiconductor substrate having a channel region between a source and a drain region, a gate structure arranged to control the channel region and a dielectric structure arranged between the channel region and the gate structure. The dielectric structure includes a high-k dielectric layer or a high-k ferroelectric layer and at least one two dimensional (2D) hexagonal boron-nitride (h-BN) layer in direct contact with the high-k dielectric layer or the high-k ferroelectric layer.

Abstract: A dispersive optical phased array for two-dimensional scanning is disclosed herein. The array comprises antenna blocks positioned adjacent one another. The antenna blocks comprise a plurality of antennas positioned adjacent one another and a plurality of delay lines to couple a coherent source signal to each of the antennas within the block, each delay line having an optical path length. Each of the antenna blocks acts as a dispersive phased array. The antenna blocks are arranged such that the blocks form a larger phased array where the antennas between the blocks are in phase for a discrete set of wavelengths. All antennas over the dispersive phased array can experience the same phase difference such that the beams of the individual antenna blocks align with one of the diffraction orders of the array of blocks.