Abstract: An example includes a field-flow fractionation device for the continuous separation of sample components including a channel comprising a sample inlet and a plurality of sample outlets, the channel being for coupling to a flow generator for translocating the sample components along the channel in a first direction from the sample inlet to the plurality of sample outlets, an actuator, which is not the flow generator, coupled to the channel, for translocating the sample components in a second direction, at a first angle with the first direction, an array of electrodes for connection to an AC power source, being in a path taken by the sample components in the channel, arranged in a plurality of rows, and in such a way that adjacent rows can be set at different potentials and every other row can be set at the same potential.

Abstract: A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred.

Abstract: A neural network circuit for providing a threshold weighted sum of input signals comprises at least two arrays of transistors with programmable threshold voltage, each transistor storing a synaptic weight as a threshold voltage and having a control electrode for receiving an activation input signal. Additionally, for each array of transistors, a reference network associated therewith, which provides a reference signal to be combined with the positive or negative weight current components of the transistors of the associated array, the reference signal having opposite sign compared to the weight current components of the associated array, thereby providing the threshold of the weighted sums of the currents. Further, at least one bitline is configured to receive the combined positive and/or negative current components, each combined with their associated reference signals.

Abstract: An apparatus for displaying a three-dimensional image comprises: a light field generating unit (110), which is configured to receive an incident light beam (112) and generate a three-dimensional light field; and an image revealing medium (120), which is arranged to receive the three-dimensional light field generated by the light field generating unit (110), wherein the image revealing medium (120) comprises a fluid with bubbles or particles suspended in the fluid, wherein the bubbles or particles have a size in the range of 40-500 nm.

Abstract: A structure is provided and includes (i) a substrate having a surface, the surface comprising a ternary or quaternary oxide having a first lattice parameter, the first lattice parameter being a lattice parameter of the ternary or quaternary oxide as it is present at the surface; and (ii) a layer of a perovskite oxide on the ternary or quaternary oxide, the perovskite oxide having a second lattice parameter, the second lattice parameter being a native lattice parameter of the perovskite oxide, wherein the first lattice parameter is larger than the second lattice parameter. A method for forming a perovskite oxide with an a-axis orientation is also provided.

Abstract: An aqueous solution for etching silicon dioxide and method of use are provided. The aqueous solution includes the anion F? in a concentration ranging from 2 to 4 mol/l and a cation of formula RR?R?R??N+ in a concentration ranging from 1.5 to 2 mol/l, wherein each of R, R?, R?, and R?? are independently selected from hydrogen and C1-5 alkyl chains with the proviso that the total number of carbon atoms in R, R?, R?, and R?? combined equals from 8 to 16.

Abstract: A wireless communication device comprises a control unit, an antenna interface, an active wireless transceiver operable together with the control unit and antenna interface, a passive wireless transceiver operable together with the antenna interface and operable by harvesting power from received radio messages. The device is further configured to deactivate the one or more active wireless transceivers and control unit to an inactive state and, subsequently, by the passive wireless transceiver, activate the control unit and an active wireless transceiver to an active state when the passive wireless transceiver receives a message from the antenna interface.

Abstract: A method for preparing a sample for transmission electron microscopy (TEM) comprises providing a substrate having a patterned area on its surface that is defined by a particular topography. A conformal layer of contrasting material is deposited on the topography by depositing a layer of the contrasting material on a local target area of the substrate, spaced apart from the patterned area via Electron Beam Induced Deposition (EBID). The deposition parameters, the thickness of the layer deposited in the target area, and the distance of the target area to the patterned area are selected so that a conformal layer of the contrasting material is formed on the topography of the patterned area. A protective layer is subsequently deposited. The protective layer does not damage the topography in the patterned area because the patterned area is protected by the conformal layer.

Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.

Abstract: In a radar system, a cancellation circuit is described for compensating for the effects of spillover between each transmitter and a receiver. The cancellation circuit is configured for applying cancellation signals to the receiver which are generated in a cancellation filter utilizing a primary impulse response characteristic corresponding to the spillover, a signal to be transmitted from each transmitter in the radar system, and a range profile output from the receiver. The cancellation circuit may also include a secondary impulse response characteristic module and a dithering module to improve the sensitivity of the receiver.

Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

Abstract: A sensor comprises: a thin structure, which is configured to receive a force for deforming a shape of the thin structure and which is arranged above a substrate; and a waveguide for guiding an electro-magnetic wave comprising: a first waveguide part; and a second waveguide part; wherein the second waveguide part has a larger width than the first waveguide part; and wherein the first and the second waveguide parts are spaced apart by a gap which is sufficiently small such that the first and second waveguide parts unitely form a single waveguide, wherein one of the first and the second waveguide part is arranged at least partly on the thin structure and another of the first and the second waveguide part is arranged on the substrate.

Abstract: A spectral sensor comprises (i) a first type of interference filter comprising reflective multilayers of a first type and an intermediate layer configured to give a constructive interference for a wavelength in a first range, and (ii) a second type of interference filter comprising reflective multilayers of a second type and an intermediate layer configured to give a constructive interference for a wavelength in a second range. The sensor further comprises first and second filter stacks configured to selectively transmit light in the first and second wavelength ranges to first and second photo-sensitive areas, respectively. The first filter stack includes the first type of interference filter and a second type of dielectric mirror that is reflective in the second wavelength range. The second filter stack includes the second type of interference filter and a first type of dielectric mirror that is reflective in the first wavelength range.

Abstract: Methods are provided for manufacturing flat devices to be used for forming a shape-retaining non-flat device by deformation of the flat device. Based on the layout of a non-flat device, a layout of a flat device is designed. A method for designing the layout of such a flat device is provided, wherein the method includes inserting mechanical interconnections between pairs of elements to define the position of the elements on a surface of the non-flat device, thus leaving zero or less degrees of freedom for the location of the components. Based on the layout of a flat device thus obtained, the flat device is manufactured and next transformed into the shape-retaining non-flat device by means of a thermoforming process, thereby accurately and reproducibly positioning the elements at a predetermined location on a surface of the non-flat device.

Abstract: An optical device (100) for forming a distribution of a three-dimensional light field comprises: an array (102) of unit cells (104), a unit cell (104) being individually addressable for switching the optical property of the unit cell (104) between a first and a second condition; wherein the unit cells (104) are configured to be selectively active or inactive and wherein the array (102) comprises at least a first and a second disjoint subset (110; 112; 114; 116), and wherein the unit cells (104) in a subset (110; 112; 114; 116) are configured to be jointly switched from inactive to active, wherein the active unit cells (104) are configured to interact with an incident light beam (106) for forming the distribution of the three-dimensional light field; and wherein the optical device (100) is configured to address inactive unit cells (104) for switching the optical property of unit cells (104).

Abstract: A sensor is provided, the sensor including a field effect transistor comprising: (a) an active region comprising: (i) a source region and a drain region defining a source-drain axis and (ii) a channel region between the source region and the drain region; (b) a dielectric region on the channel region, comprising at least a first zone on a first portion of the channel region and a second zone on a second portion of the channel region, the first zone measuring from 1 to 100 nm in the direction of the source-drain axis and being adapted to create a different threshold voltage for the first portion of the channel region than for the second portion of the channel region, and (c) a fluidic gate region to which a top surface of the dielectric region is exposed. A biosensing device comprising such a sensor, a method for using such a sensor, and a process for making such a sensor are also provided.

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to three-dimensional semiconductor devices. In one aspect, a method of manufacturing a three-dimensional (3D) semiconductor device includes providing a horizontal layer structure above a substrate and forming an opening that extends vertically through the horizontal layer structure to the substrate. The method additionally includes lining an inside vertical surface of the opening with a gate stack and lining the inside vertical surface of the opening having the gate stack formed thereon with a sacrificial material layer. The method additionally includes filling the opening with a filling material and removing the sacrificial material layer to form a recess. The method further includes forming the channel by epitaxially growing, in the recess, a channel material upwards from the substrate.

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell

Abstract: A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.