Patents Assigned to IMEC
  • Patent number: 11381242
    Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: July 5, 2022
    Assignee: IMEC VZW
    Inventors: Francky Catthoor, Edouard Giacomin, Juergen Boemmels, Julien Ryckaert
  • Patent number: 11374058
    Abstract: The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (?B) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (?T) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 28, 2022
    Assignee: IMEC vzw
    Inventors: Shairfe Muhammad Salahuddin, Alessio Spessot
  • Patent number: 11372158
    Abstract: A waveguide for guiding an electro-magnetic wave comprises: a first waveguide part; and a second waveguide part; wherein the first waveguide part has a first width in a first direction (Y) perpendicular to the direction of propagation of the electro-magnetic wave and the second waveguide part has a second width in the first direction (Y), wherein the second width is larger than the first width; and wherein the first and the second waveguide parts are spaced apart by a gap in a second direction (Z) perpendicular to the first and second planes in which the waveguide parts are formed, wherein the gap has a size which is sufficiently small such that the first and second waveguide parts unitely form a single waveguide for guiding the electro-magnetic wave. The waveguide may be used in numerous applications, such as in a photonic integrated circuit, in a sensor or in an actuator.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: June 28, 2022
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN
    Inventors: Wouter Jan Westerveld, Veronique Rochus, Simone Severi, Roelof Jansen
  • Patent number: 11369275
    Abstract: A device for read-out of a photoplethysmography (PPG) signal comprises: a photodiode, which is configured to detect a PPG signal, the photodiode comprising a first and a second terminal; and a read-out circuitry for reading out the PPG signal, wherein an input stage is connected to receive a first and a second input signal from the terminals and a DC bias voltage, and wherein the input stage is configured for current sensing to provide a fully differential amplification of the input signals to a first and a second current signal, and wherein an output stage is configured to receive the current signals, wherein the current signals comprise an AC and a DC component of the PPG signal, and wherein the output stage is configured to generate a differential output voltage through a gain component.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: June 28, 2022
    Assignees: IMEC VZW, STICHTING IMEC NEDERLAND
    Inventors: Shuang Song, Jiawei Xu, Roland Van Wegberg, Nick Van Helleputte
  • Patent number: 11371959
    Abstract: A device and a method for performing an assay is provided. The assay device, which may be used for determining the concentration of an analyte in a sample, includes a plurality of microchambers and a Field-effect transistor (FET) arranged at the bottom of each of the plurality of microchambers. Capture probe molecules for the analyte can be arranged within the plurality of microchambers such that each microchamber contains at most one capture probe molecule. The FET can be arranged in said microchamber to give a readable output signal based on binding of the analyte, or competitor to the analyte, with the capture probe molecule.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 28, 2022
    Assignee: IMEC VZW
    Inventors: Kris Covens, Karolien Jans, Koen Martens
  • Patent number: 11367251
    Abstract: The disclosed technology presents a device and a method, respectively, for generating an augmented reality (AR) image (or AR video). The device configures to obtain a first image of a scene, obtain a second image of an object, obtain a depth range, and capture a third image of only the parts of the scene inside the depth range. Further, the device configures to generate occlusion information based on the third image, and overlay the first image and the second image based on the occlusion information to generate the AR image.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: June 21, 2022
    Assignee: IMEC vzw
    Inventor: Maarten Rosmeulen
  • Patent number: 11367705
    Abstract: A method of using sacrificial structures in a mold substrate for packaging a first die and one or more second dies or stacks thereof is disclosed. The method allows testing of the first die prior to mounting the second dies, without requiring a TSV insert. In one aspect, a block of sacrificial material is embedded together with the first die in a first mold substrate and to one side of the first die. The removal of the block creates an opening. The method is configured so that contacts are exposed at the bottom of the opening, the contacts being electrically connected to corresponding contacts on the first die. This may be realized by bonding both the die and the sacrificial block to a redistribution layer, or by mounting a bridge device between the first die and the block prior to a first overmolding applied for producing the first mold substrate.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 21, 2022
    Assignee: IMEC vzw
    Inventor: Eric Beyne
  • Patent number: 11367797
    Abstract: In a first aspect, the present invention relates to a nanopore field-effect transistor sensor (100), comprising: i) a source region (310) and a drain region (320), defining a source-drain axis; ii) a channel region (330) between the source region (310) and the drain region (320); iii) a nanopore (400), defined as an opening in the channel region (330) which completely crosses through the channel region (330), oriented at an angle to the source-drain axis, having a first orifice (410) and a second orifice (420), and being adapted for creating a non-linear potential profile between the first (410) and second (420) orifice.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 21, 2022
    Assignee: IMEC VZW
    Inventors: Chang Chen, Koen Martens, Pol Van Dorpe, Simone Severi
  • Patent number: 11368164
    Abstract: An interleaver for combining at least two incoming signals into an analog output signal includes at least a first signal path and a second signal path. Each signal path has: an input terminal, a first gain stage for multiplying a signal coming from the input terminal with a first gain (a) to obtain a first signal, a mixer and a second gain stage for multiplying a signal coming from the input terminal with a second gain (b) before or after mixing it with a clock signal to obtain a second signal, an adder for adding the first and second signal to obtain an output signal of the signal path wherein the first and second gain are different from zero. The interleaver comprises an adder for adding the output signals from the signal paths.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 21, 2022
    Assignees: UNIVERSITEIT GENT, IMEC VZW
    Inventors: Guy Torfs, Hannes Ramon, Xin Yin
  • Patent number: 11366060
    Abstract: An apparatus for detecting fluorescent light emitted from a sample comprises: a light source, which is configured to emit excitation light of an excitation wavelength towards a sample comprising fluorophores such that fluorescent light is induced; a photo-detector for detecting light incident on the photo-detector; and an interference filter arranged on the photo-detector, wherein the interference filter is configured to selectively collect and transmit light towards the photo-detector based on an angle of incidence of the light towards the interference filter, wherein the interference filter is configured to selectively transmit supercritical angle fluorescence from the sample towards the photo-detector and suppress undercritical angle fluorescence from the sample.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 21, 2022
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN
    Inventors: Finub James Shirley, Pol Van Dorpe
  • Publication number: 20220190352
    Abstract: A method (100) for making a non-aqueous rechargeable metal-air battery is provided. The method includes before and/or after inserting (108) a cathode in the battery, a pre-conditioning step (104, 106, 110) of a 3D nanomesh structure, so as to obtain a pre-conditioned 3D nanomesh structure, the pre-conditioned 3D nanomesh structure being free of cathode active material. A cathode to be inserted into a non-aqueous rechargeable metal-air battery is also provided. The cathode includes a pre-conditioned 3D nanomesh structure made of nanowires made of electronic conductive metal material, the pre-conditioned 3D nanomesh structure being free of cathode active material. A non-aqueous rechargeable metal-air battery including such a cathode is also provided.
    Type: Application
    Filed: April 1, 2019
    Publication date: June 16, 2022
    Applicants: Toyota Motor Europe, IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN
    Inventors: Fanny Jeanne Julie BARDE, Philippe VEREECKEN, Yongho KEE
  • Patent number: 11360380
    Abstract: The present disclosure relates to an extreme ultraviolet lithography, EUVL, device comprising: a reticle comprising a lithographic pattern to be imaged on a target wafer; a light-transmissive pellicle membrane mounted in front of, and parallel to, the reticle, wherein the pellicle membrane scatters transmitted light along a scattering axis; and an extreme ultraviolet, EUV, illumination system configured to illuminate the reticle through the pellicle membrane, wherein an illumination distribution provided by the EUV illumination system is asymmetric as seen in a source-pupil plane of the EUV illumination system; wherein light reflected by the reticle and then transmitted through the pellicle membrane comprises a non-scattered fraction and a scattered fraction formed by light scattered by the pellicle membrane; the EUVL device further comprising: an imaging system having an acceptance cone configured to capture a portion of the light reflected by the reticle and then transmitted through the pellicle membrane.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 14, 2022
    Assignee: IMEC VZW
    Inventors: Joern-Holger Franke, Emily Gallagher
  • Patent number: 11360262
    Abstract: An integrated wavelength-selective filter device comprises a first optical element, for directing received radiation into a direction defined by a first angle, and a second optical element being a diffractive element configured for diffracting the directed radiation under a second angle. The second angle is such that for a single reference wavelength the diffracted radiation is directed into a propagation medium for advancing therein towards a predetermined position on the first optical element or on a further optical element for filtering radiation having a wavelength substantially matching the reference wavelength from radiation having a substantially different wavelength. The propagation medium is formed from a material that is different from any material of the substrate of the first and the second optical element.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: June 14, 2022
    Assignees: UNIVERSITEIT GENT, IMEC VZW
    Inventors: Roeland Baets, Eva Ryckeboer, Abdul Rahim, Anton Vasiliev, Xiaomin Nie
  • Patent number: 11362195
    Abstract: A semiconductor device and a method for forming such are provided, the device including: a substrate, a plurality of parallel active semiconductor patterns that extend through a drain-side region and a source-side region, a metal drain contact in the drain-side region, an active gate pattern, a first dummy gate pattern, and a second dummy gate pattern that all extend across the active semiconductor patterns, and a metal interconnect structure located in a region between the first and the second dummy gate patterns. The active semiconductor patterns are doped with a dopant in portions exposed by the dummy gates in dummy gate regions that include the gate cut regions of the first and second dummy gate patterns. The metal interconnect structure connects each of a second subset of the active semiconductor patterns to a respective at least one of a first subset of the active semiconductor patterns.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 14, 2022
    Assignee: Imec VZW
    Inventors: Shih-Hung Chen, Dimitri Linten
  • Patent number: 11362061
    Abstract: A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: June 14, 2022
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Lin Hou, Jaber Derakhshandeh, Eric Beyne, Ingrid De Wolf, Giovanni Capuz
  • Patent number: 11358144
    Abstract: A micro-fluidic device is provided to sort out objects from a liquid stream. The device comprises a first channel comprising a first liquid and a second channel comprising a second liquid and the first liquid, and a third channel. The second channel is connected to the first channel and the channels are positioned such that a jet flow coming from the second channel can deflect objects in the first liquid into the third channel. The first liquid is a liquid which has a higher viscosity than water and the second liquid may be the same as or different from the first liquid. The micro-fluidic device is adapted for generating the jet flow in the second liquid.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 14, 2022
    Assignee: IMEC VZW
    Inventors: Chengxun Liu, Rodrigo Sergio Wiederkehr
  • Patent number: 11355618
    Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 7, 2022
    Assignee: IMEC VZW
    Inventors: Abhitosh Vais, Liesbeth Witters, Yves Mols
  • Patent number: 11351539
    Abstract: A multi-level microfluidic device is provided. The device includes a silicon wafer substrate and a stack of layers arranged on the silicon wafer substrate. The stack comprises a plurality of fluidic silicon layers, wherein each fluidic silicon layer includes a microfluidic structure at least one intermediate layer. The at least one intermediate layer is arranged between two fluidic silicon layers, and a fluid inlet and a fluid outlet in fluid connection with at least one of the fluidic silicon layers. Each layer in the stack is formed by deposition or growth. Methods for manufacturing microfluidic devices is also provided.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 7, 2022
    Assignee: IMEC VZW
    Inventor: Silvia Lenci
  • Patent number: 11350866
    Abstract: A read-out circuitry for acquiring a multi-channel biopotential signal, comprises: a plurality of read-out signal channels, each receiving an input signal from a unique signal electrode; a reference channel receiving a reference signal from a reference electrode; wherein each read-out signal channel and the reference channel comprises a channel amplifier connected to receive the input signal in a first input node and with an output node connected to a second input node via a channel feedback loop; wherein each signal channel amplifier comprises a capacitor between the second input nodes of the signal channel amplifier and the reference channel amplifier, and wherein each signal channel feedback loop and the reference channel feedback loop comprise a filter.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: June 7, 2022
    Assignees: STICHTING IMEC NEDERLAND, IMEC VZW
    Inventors: Roland Van Wegberg, Wim Sijbers
  • Patent number: 11356061
    Abstract: The method of calibrating a two-point modulation phase locked loop (PLL) comprises observing, between the loop filter and the second injection point, the loop control signal over at least one period of the first periodic control signal; generating, from the observed loop control signal, a distortion profile; and applying the distortion profile to the second periodic control signal before injecting the second periodic control signal in the PLL. Since, in the case of non-linearity in the controlled oscillator, the PLL output deviates from the ideally expected one, cancellation through the first injection point becomes imperfect disturbing the loop. This error pattern can be observed on the loop filter which allows to generate a distortion profile to distort the second periodic control signal for the next period of the modulation. This will mitigate the effects of the non-linearity of the oscillator.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: June 7, 2022
    Assignee: IMEC VZW
    Inventors: Nereo Markulic, Jan Craninckx, Miguel Glassee