Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions.

Abstract: The disclosed technology generally relates to semiconductor devices and methods of manufacturing semiconductor devices such as both logic and memory semiconductor devices. In one aspect, a semiconductor device includes a semiconductor substrate having a channel region between a source and a drain region, a gate structure arranged to control the channel region and a dielectric structure arranged between the channel region and the gate structure. The dielectric structure includes a high-k dielectric layer or a high-k ferroelectric layer and at least one two dimensional (2D) hexagonal boron-nitride (h-BN) layer in direct contact with the high-k dielectric layer or the high-k ferroelectric layer.

Abstract: A dispersive optical phased array for two-dimensional scanning is disclosed herein. The array comprises antenna blocks positioned adjacent one another. The antenna blocks comprise a plurality of antennas positioned adjacent one another and a plurality of delay lines to couple a coherent source signal to each of the antennas within the block, each delay line having an optical path length. Each of the antenna blocks acts as a dispersive phased array. The antenna blocks are arranged such that the blocks form a larger phased array where the antennas between the blocks are in phase for a discrete set of wavelengths. All antennas over the dispersive phased array can experience the same phase difference such that the beams of the individual antenna blocks align with one of the diffraction orders of the array of blocks.

Abstract: An imaging sensor comprises: an array of light-detecting elements, wherein each light-detecting element in the array of light-detecting elements is arranged in the imaging sensor so as to detect a respective wavelength interval, wherein the respective wavelength interval differs for different light-detecting elements; a pattern arranged on the array of light-detecting elements, wherein the pattern defines a plurality of transparent areas, each transparent area being associated with a corresponding light-detecting element in the array of light-detecting elements, wherein a size of a transparent area among the plurality of transparent areas is dependent of the corresponding light-detecting element with which the transparent area is associated.

Abstract: A photonic integrated circuit comprises an input interface adapted for receiving an optical input signal and splitting it into two distinct polarization modes and furthermore adapted for rotating the polarization of one of the modes for providing the splitted signals in a common polarization mode. The PIC also comprises a combiner adapted for combining the first mode signal and the second mode signal into a combined signal and a decohering means adapted for transforming at least one of the first mode signal and the second mode signal such that the first mode signal and the second mode signal are received by the combiner in a mutually incoherent state. A processing component for receiving and processing said combined signal is also comprised.

Abstract: A communication system comprising: input buffers adapted for buffering incoming data streams of samples from one or more channels; a receiver adapted for sequentially processing data from the input buffers; a processing rate of the receiver is higher than or equal to an incoming data rate of the incoming data; context memory adapted for saving an internal status of the receiver after processing the data corresponding with an input buffer before switching to a next input buffer and for restoring the internal status, wherein the receiver is adapted for processing the incoming data in a frame detection phase, and in a frame demodulation phase in which frames and/or subframes are demodulated into bits and wherein the internal status of the receiver related to an input buffer is only saved and restored in the frame detection phase or before and after demodulating subframes.

Abstract: The present disclosure relates to devices and methods for analyzing a fluid sample. An example device comprises a fluidic substrate comprising a micro-fluidic component embedded therein, for propagating a fluid sample; a needle or inlet for providing the fluid sample which is fluidically connected to the micro-fluidic component; a lid attached to the fluidic substrate thereby at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component; wherein the fluidic substrate is a glass fluidic substrate and wherein the lid is a microchip. The present disclosure also relates to a method for fabricating a fluid analysis device. The method comprises providing a fluidic substrate; providing a lid; attaching the lid to the fluidic substrate to close the fluidic substrate at least partly.

Abstract: A computer-implemented method comprises obtaining an intermediate computer code object including a set of instructions corresponding to a task to be performed. The intermediate computer code object—being machine independent—further includes for each of the at least one set of instructions one or more metadata descriptors representative of at least a complexity measure of the task to be performed. The method also comprises executing the intermediate computer code object on a computing platform comprising at least two different execution units having a different memory with a different memory location. This executing comprises selecting for each of the at least one set of instructions a target execution unit from the plurality of execution units. This selecting takes the one or more metadata descriptors and a decision rule into account, wherein the decision rule relates the plurality of complexity measures to a performance characteristic of the plurality of execution units.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs.

Abstract: Example embodiments relate to single-photon avalanche diode detector (SPAD) arrays. One embodiment includes a SPAD array that includes a silicon substrate, a plurality of primary electrodes, and a plurality of secondary electrodes. Each of the primary electrodes includes a semiconductor material of a first doping type, extends in the silicon substrate in a first direction, and has a rotationally symmetric cross-section in a first plane perpendicular to the first direction. The plurality of secondary electrodes includes a semiconductor material of a second doping type and extends parallel to the primary electrodes in the silicon substrate. Further, the silicon substrate includes a doped upper field redistribution layer, a doped lower field redistribution layer, and a doped depletion layer arranged between the upper field redistribution layer and the lower field redistribution layer.

Abstract: A device is configured to monitor a state of a rotatable handle of a valve when the device is attached to the rotatable handle. The device comprises a vector magnetometer configured to measure a magnetic field. The device comprises a processing unit configured to obtain from the vector magnetometer measurements of the magnetic field when the handle is rotated; calculate a change in the state of the rotatable handle based on a difference between the measurements of the magnetic field; and report the change in the state.

Abstract: A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

Abstract: The present invention relates to a method for integrating an electronic circuit in or on a medical stent. The method comprises obtaining (101) a deformable medical stent (21) in a substantially planar shape, in which the deformable medical stent is adapted for being deployed in a substantially cylindrical shape in the body. The method also comprises attaching (104) a deformable electronic circuit (22) onto the deformable medical stent in the planar shape thereby forming a deformable hybrid structure. The method also comprises shaping (107) said hybrid structure into the cylindrical shape.

Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

Abstract: A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segme

Abstract: The disclosure provides methods and systems for analyzing fluid samples comprising obtaining fluid samples in at least one cavity of a substrate and introducing also buffers and/or reagents in the cavity, performing nucleic acid extraction and/or purification in the cavity, and performing nucleic acid amplification in the same cavity.

Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

Abstract: The disclosed technology generally relates to a memory device, and more particularly to a ferroelectric memory device and a method of operating the memory device. According to one aspect, a memory device comprises a bit cell. The bit cell comprises a write transistor, a read transistor and a ferroelectric capacitor. A write word line is connected to a gate terminal of the write transistor. A write bit line is connected to a first terminal of the write transistor. A read bit line connected to a terminal of the read transistor. A first control line is connected to a first electrode of the ferroelectric capacitor. A second terminal of the write transistor is connected to the gate terminal of the read transistor, and a second electrode of the ferroelectric capacitor is connected to the second terminal.

Abstract: At least one embodiment relates to a focusing arrangement for focusing particles or cells in a flow. The arrangement includes at least one channel for guiding the flow. The channel includes (i) at least one particle confinement structure having particle flow boundaries and (ii) at least one acoustic confinement structure having acoustic field boundaries adapted for confining acoustic fields. The acoustic field boundaries may be different from the particle flow boundaries, and the at least one acoustic confinement structure may be arranged with regard to the channel to at least partially confine acoustic fields in the channel.