Abstract: A method for forming a heterojunction bipolar transistor is provided. The method includes (a) forming a doped region in a group IV semiconductor layer of a substrate; (b) forming an epitaxially grown III-V semiconductor body on a surface portion of the doped region, the body extending from the surface portion and protruding vertically above the doped region, wherein the doped region and the body forms a first sub-collector part and a second sub-collector part, respectively; and (c) forming an epitaxially grown III-V semiconductor layer stack on the body, the layer stack comprising a collector, a base and an emitter. There is further provided a heterojunction bipolar transistor device.

Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

Abstract: The present disclosure relates to a lithography scanner including: a light source configured to emit extreme ultra-violet (EUV) light; a pellicle including an EUV transmissive membrane that is configured to scatter the EUV light into an elliptical scattering pattern having a first major axis; a reticle configured to reflect the scattered EUV light through the pellicle; and an imaging system configured to project a portion of the reflected light that enters an acceptance cone of the imaging system onto a target wafer, wherein a cross section of the acceptance cone has a second major axis, and wherein the pellicle is arranged such that the first major axis is oriented at an angle relative to the second major axis.

Abstract: Example embodiments relate to methods for adjusting an impedance of a tunable matching network, One embodiment includes a method for adjusting an impedance of a tunable matching network (TMN) connected between an antenna and a transceiver front-end. The TMN includes a receive path to provide signals from the antenna to a receiver during a receive (Rx) mode and a transmit path to provide signals from a transmitter to the antenna during a transmit (Tx) mode. The method includes tuning the TMN. The method also includes measuring values of an output DC-offset at the receiver while tuning the TMN. The output DC-offset is caused by a coupling between the transmitter and the receiver. Further, the method includes determining a maximum value of the output DC-offset from the measured output DC-offset values. Additionally, the method includes adjusting the impedance of the TMN by tuning the TMN to the output DC-offset maximum value.

Abstract: A measuring system includes a first measuring device and a second measuring device. The measuring system is configured to, between the first measuring device and the second measuring device, determine a first phase shift at a first frequency, determine a second phase shift at a second frequency, and determine a third phase shift at a third frequency. The first measuring device includes a phase difference calculator configured to calculate a first phase difference between the first phase shift and the second phase shift, and a second phase difference between the second phase shift and the third phase shift. The first measuring device also includes a range/velocity calculator configured to determine a first biased distance estimate from the first phase difference, a second biased distance estimate from the second phase difference, and an unbiased distance and/or velocity from the first biased distance estimate and the second biased distance estimate.

Abstract: Example embodiments relate to methods and imaging systems for holographic imaging. One embodiment includes a method for holographic imaging of an object. The method includes driving a laser using a current which is below a threshold current of the laser. The method also includes illuminating the object using illumination light output by the laser. Further, the method includes detecting an interference pattern formed by object light, having interacted with the object, and reference light of the illumination light.

Abstract: A multi-chip system is configured as an antenna array. The multi-chip system includes at least two transmitting sets distributed over one or more transmitting chips, where the transmitting sets each include an integrated transmitting antenna and an integrated up-conversion circuit. The multi-chip system further includes at least two receiving chips, where the receiving chips each include at least one integrated receiving antenna and at least one integrated down-conversion circuit.

Abstract: The disclosed technology generally relates semiconductor devices, and relates more particularly to a spin transfer torque device, a method of operating the spin-transfer torque device and a method of fabricating the spin-transfer torque device. According to one aspect, a spin-transfer torque device includes a magnetic flux guide layer and a set of magnetic tunnel junction (MTJ) pillars arranged above the magnetic flux guide layer. Each one of the pillars includes a separate free layer, a separate tunnel barrier layer and a separate reference layer. A coupling layer is arranged between the magnetic flux guide layer and the MTJ pillars, wherein a magnetization of the separate free layer of each of the each of the MTJ pillars is coupled, parallel or antiparallel, to a magnetization of the magnetic flux guide layer through the coupling layer.

Abstract: An integrated photonic device may include an image detector that comprises an array of pixels. The device may further include an integrated waveguide and a light coupler comprising a light receiving part optically coupled to the integrated waveguide for receiving a light signal. The light coupler may be adapted for coupling a same predetermined spectral band of the light signal to each of a plurality of pixels of the image detector. The light coupler may include a tapered portion, in which the light coupler tapers outward in a direction of propagation, and an end part comprising an elliptically shaped back reflector for reflecting light propagating along the direction of propagation back through the light coupler toward the integrated waveguide.

Abstract: Disclosed herein is a system for determining a subject's stress condition. The system includes a stress test unit configured for: receiving features defining the subject and physiological signals sensed from the subject when performing a relaxation and a stressful test task; extracting normalization parameters from the physiological signals; and identifying stress-responsive physiological features. The system also includes a storage unit configured for: storing a plurality of stress models; and storing the subject's features, normalization parameters, and the stress-responsive physiological features.

Abstract: A circuit for correlated double sampling is disclosed. In one aspect, the circuit comprises a reset switch connected with an input node, and with a first node of a first capacitor; a sampling switch connected with the input node, and with a first node of a second capacitor; a second node of the first/second capacitor is adapted to be connected with a first/second reference node, of which at least one using a reference switch; a first switch connected between the second node of the first capacitor and the first node of the second capacitor; a second switch connected between the first node of the first capacitor and the second node of the second capacitor.

Abstract: A method includes depositing a first layer including amorphous silicon on a surface of a substrate; depositing a second layer including metal on the first layer; and performing an annealing process at a temperature within a range of 70° C. to 200° C., thereby inducing a silicidation reaction between the first layer and the second layer and forming a third layer comprising a metal silicide in electrical contact with the substrate, resulting in a remaining part of the first layer being between the substrate and the third layer.

Abstract: The disclosed technology generally relates to magnetic devices and more particularly to magnetic tunnel junction (MTJ) devices in which switching can be mediated by spin-orbit torque, and further relates to a method of fabricating such devices. In an aspect, a magnetic tunnel junction (MTJ) device includes a spin-orbit torque (SOT) mediating layer, a hard-mask layer used to define a shape of the SOT layer, a magnetic tunnel junction arranged between the SOT layer and the hard-mask layer. The MTJ includes at least a free layer and a reference layer separated by a non-magnetic barrier layer. The device further includes at least two electrical accesses arranged to contact the SOT layer to pass a write current therethrough. To provide field-free switching of the free layer, the device further includes a ferromagnetic element as at least one of a ferromagnetic sublayer of the hard-mask and a material in the electrical accesses.

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second nanosheet transistor structure, each comprising a source, a drain, and a channel extending between the source and the drain in a first direction, and a gate extending across the channel, wherein the first and second nanosheet transistor structures are spaced apart in a second direction, transverse to the first direction, by an insulating wall extending in the first direction.

Abstract: A method for protecting a photomask comprises: (i) providing the photomask, (ii) providing a border, (iii) depositing at least two electrical contacts on the border, (iv) mounting a film comprising carbon nanotubes on the border such that the film comprises a free-standing part, wherein after the mounting and depositing steps, the electrical contacts are in contact with the film, (v) inducing a current through the free-standing part of the film by biasing at least one pair of the electrical contacts, and (vi) mounting the border on at least one side of the photomask with the free-standing part of the film above the photomask.

Abstract: A semiconductor detector (100) for electromagnetic radiation within a wavelength range is disclosed, comprising a first waveguide portion (110), a funnel element (130) configured to funnel incident electromagnetic radiation into a first end (112) of the first waveguide portion, and a second waveguide portion (120) extending in parallel with the first waveguide portion. The second waveguide portion is coupled to the first waveguide portion and configured to out-couple electromagnetic radiation from the first waveguide portion, within a sub-range of the wavelength range. Further, a photodetector (140) including a photoactive layer (144) is arranged at a second end (114) of the first waveguide portion and at an end (124) of the second waveguide portion, and configured to separately detect electromagnetic radiation transmitted through and exiting the first waveguide portion and the second waveguide portion.

Abstract: A pipelined successive approximation register analog-to-digital converter (2), SAR ADC, comprises a first SAR ADC stage (4); an inter-stage amplifier (6) for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage (8) input from the inter-stage amplifier, wherein the inter-stage amplifier (6) comprises one or more MOS transistors (16, 18), wherein the source and drain terminals of each of the one or more MOS transistors (16, 18) are connected to each other and may be toggled between ground and a supply voltage.

Abstract: A fluidic device is described for locally coating an inner surface of a fluidic channel. The fluidic device comprises a first, a second and a third fluidic channel intersecting at a common junction. The first fluidic channel is connectable to a coating fluid reservoir and the third fluidic channel is connectable to a sample fluid reservoir. The fluidic device further comprises a fluid control means configured for creating a fluidic flow path for a coating fluid at the common junction such that, when coating, a coating fluid propagates from the first to the second fluidic channel via the common junction without propagating into the third fluidic channel. A corresponding method for coating and for sensing also has been disclosed.

Abstract: A device is provided for electrically measuring surface characteristics of a sample. The device comprises at least one group of three electrodes: a first and second electrode spaced apart from each other and configured to be placed onto the surface of the sample, and a third electrode between the first two but isolated from these two electrodes by a one or more first insulators, wherein a second insulator further isolates the central electrode from the sample when the device is placed thereon. The three electrodes and the insulators are attached to a single or to multiple holders with conductors incorporated therein for allowing the coupling of the electrodes to power sources or measurement tools. The placement of the device onto a semiconductor sample creates a transistor with the sample surface acting as the channel. The device thereby allows the determination of the transistor characteristics of the sample in a straightforward way.