Abstract: A monolithic half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.

Abstract: A digital microphone includes a log amplifier having an input for receiving an analog signal; an analog-to-digital converter (ADC) coupled to the log amplifier; a digital low-pass filter coupled to the ADC; a digital decompression component coupled to the digital low-pass filter; and a predictor filter coupled to the digital decompression component, the predictor filter having an output for generating a digital signal. The digital low-pass filter is a positive group delay filter and the predictor filter is a negative group delay filter. The digital microphone has an improved Signal-to-Noise Ratio (SNR) due to filtering, but without increasing overall group delay.

Abstract: This disclosure includes multiple assemblies, sub-assemblies, etc., as well as one or more methods of fabricating same. For example, a first assembly includes a first circuit board. The first circuit board further includes first connector elements disposed on a first edge of the first circuit board and second connector elements disposed on a second edge of the first circuit board. The first edge may be disposed substantially opposite the second edge on the first circuit board. The apparatus may further include first circuitry affixed to the first circuit board. The first edge of the first circuit board aligns with a first axial end of the first circuitry and the second edge of the first circuit board aligns with a second axial end of the first circuitry. The first assembly is used to fabricate a second assembly.

Abstract: A current sensor includes a current rail and a magnetic field sensor. The magnetic field sensor is configured to measure a magnetic field induced by a current flowing through the current rail. A first insulation layer and a second insulation layer are arranged between the current rail and the magnetic field sensor. An interface between the first insulation layer and the second insulation layer is free of a contact with the current rail and/or is free of a contact with the magnetic field sensor. A portion of the current rail extends into the second insulation layer and the portion of the current rail is encapsulated by the second insulation layer.

Abstract: A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

Abstract: A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.

Abstract: An isolated DC/DC converter includes: a transformer having a primary side and a secondary side; an inverter configured to change a DC input voltage (Vin) to an AC current for energizing the primary side of the transformer; a capacitor in series with the primary side of the transformer; and a controller configured to operate the inverter in a first mode such that the capacitor pre-charges to |Vin| before the controller receives a turn ON command, the capacitor charges to X*|Vin| during a first part of a first switching cycle after the controller receives the turn ON command where X>1, and the capacitor voltage resonates with a magnetizing inductance of the primary side of the transformer during a second part of the first switching cycle. A power electronics device that includes the isolated DC/DC converter is also described.

Abstract: The present disclosure relates to a magnetic field sensor, in particular an angle sensor, including a magnetoresistive sensor component and a spin-orbit torque, SOT, sensor component.

Abstract: An interconnect connects a first device running a first application and with a first interface and a second device running a second application and with a second interface. The first device has a safety guard which may be used in an operations mode to send safety relevant data from the first application to the second application. Safety information is added to the safety relevant data to create safety marked data. The safety marked data is transmitted to the second application. The safety marked data is also looped back through interconnect to the safety guard which checks the loop back data using the safety information in the loop back data, and when the checking indicates an error, transmits an error notification signal to the first application and/or the second application.

Abstract: A package and method is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, and an encapsulant at least partially encapsulating the electronic component and partially encapsulating the carrier. At least a portion of a bottom surface and at least a portion of a sidewall of the carrier are exposed beyond the encapsulant. Said at least portion of the bottom surface and said at least portion of the sidewall are covered at least partially by a plating structure.

Abstract: A semiconductor device includes a semiconductor body having an active region and a substrate region that is disposed beneath the active region, and a bidirectional switch formed in the semiconductor body. The bidirectional switch includes first and second gate structures that are each configured to control a conductive state of an electrically conductive channel that is disposed in the active region, and first and second input-output terminals that are each in ohmic contact with the electrically conductive channel. A passive substrate voltage discharge circuit in parallel with the bidirectional switch is configured to discharge a voltage of the substrate region in both directions of the bidirectional switch. The passive substrate voltage discharge circuit includes first and second normally-on switches connected in anti-series between the first and second input-output terminals in a common source configuration with the substrate region as a midpoint.

Abstract: A circuit includes a switching signal generator and synchronization circuitry configured to determine a first time of a switching period based on a switching signal. The circuit further includes a comparison signal generator configured to generate a comparison signal with a first constant rate of change after the first time. The synchronization circuitry is further configured to determine a second time of the switching period based on when current at the inductive element changes from a positive current to a negative current. The comparison signal generator is further configured to generate the comparison signal with a second constant rate of change after the second time. The circuit further includes a threshold detector configured to compare a value of the comparison signal at the end of a target switching period with a threshold value.

Abstract: A semiconductor device includes a semiconductor die including a first side and an opposing second side, a first metallization layer arranged on the first side, a Ni including layer arranged on the second side, wherein the Ni including layer further includes one or more of Si, Cr and Ti, and a SnSb layer arranged on the Ni comprising layer, wherein an amount of Sb in the SnSb layer is in the range of 2 wt % to 30 wt %.

Abstract: A wallet including an electronic data storage unit for storing wallet information, and a data interface configured to provide a read access to the electronic data storage unit. A controller of the wallet is configured to control the wallet at a first point in time in a first operating mode, in which there is a restriction for the read access to the wallet information, and to control the wallet at a later second point in time in a second operating mode, in which the restriction to the read access is cancelled. The transition from the first operating mode to the second operating mode is irreversible.

Abstract: A lateral high-voltage transistor includes a semiconductor substrate, a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary, a dielectric layer arranged over the semiconductor substrate, and a structured gate layer arranged over the dielectric layer. The structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer. The lateral boundary of the body region is a boundary defined by dopant implantation.

Abstract: An apparatus may include an input pin\ and timing control circuitry coupled to the input pin. The timing control circuitry selectively executes one or more timing control functions based on a set of one or more hardware components coupled to the input pin. The set of one or more hardware components are disposed external to the apparatus. A configuration of the set of one or more hardware components determines which of one or more of the multiple timing control functions are enabled.

Abstract: An integrated circuit that is capable of bidirectional communication with an external host device via various communication protocols. In order to determine which communication protocols the incoming signal is using, the integrated circuit further includes an interface detector. When the interface detector determines that the incoming signal represents a portion of a transaction that uses a first communication protocol, the integrated circuit permits the first communication protocol engine to communicate in the transaction. Likewise, when the interface detector determines that the incoming signal represents a portion of a transaction that uses the second communication protocol, the integrated circuit permits the second communication protocol engine to communicate in the transaction. This allows the integrated circuit to detect the protocol regardless of whether one or two package terminals are used in the protocol.

Abstract: A device includes a safety domain having a processing unit and a memory and is configured to provide at least one functionality and to implement one more safety measures for detecting faults. The safety domain is configured to transmit at least one alarm signal indicating one or more detected errors in response to detecting the faults. The device further includes a security domain having a processing unit and a memory and is configured to provide cryptographic services and to obtain alarm signals. The security domain is configured to perform security-related operations in a secure state in response to obtaining an alarm signal from the safety domain.

Abstract: A method for producing an edge structure of a semiconductor component includes: providing a semiconductor body having at least two mutually spaced-apart main faces respectively having an edge, between which edges an edge face extends; and etching a predetermined edge contour by purposely applying a chemical etchant onto the edge face by an etchant jet with simultaneous rotation of the semiconductor body about a rotation axis. The etchant jet is guided with a predetermined jet cross section, while being directed tangentially with respect to the edge face, such that the etchant jet impinges on the edge face only with a part of the jet cross section. A corresponding device for producing an edge structure of a semiconductor component is also described.