Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.

Abstract: An ion shuttling system includes a plurality of first electrodes connected to a system configured to selectively provide an ion movement control voltage to each electrode of the plurality of first electrodes, a voltage source configured to provide one or more compensation voltages, a plurality of compensation electrodes comprising a plurality of compensation electrode pairs, where each compensation electrode pair of the plurality of compensation electrode pairs is associated with one or more different first electrodes of the plurality of first electrodes, and a plurality of switches, where each switch of the plurality of switches is connected at a respective first node to a compensation electrode of the plurality of compensation electrodes and is configured to selectively connect the respective compensation electrode to the voltage source.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: A multiphase inverter apparatus includes: an insulating substrate; at least one low voltage bus and at least one high voltage bus on a first surface of the insulating substrate; a plurality of half-bridge circuits, each half-bridge circuit being electrically coupled between a respective one of the at least one low voltage bus and a respective one of the at least one high voltage bus; and a phase output lead for each half-bridge circuit. For each half bridge circuit, the phase output lead is arranged on and electrically coupled to at least one packaged low side switch and at least one packaged high side switch of the half bridge circuit such that each packaged low side switch and each packaged high side switch is arranged vertically between the phase output lead and the first surface of the insulating substrate.

Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.

Abstract: UWB Antenna comprising: a first substrate layer (10); a second substrate layer (20); a conductive ground layer (300) arranged on a first side of the first substrate layer and connected to a ground terminal; a first conductive layer (100) arranged between the first substrate layer (10) and the second substrate layer (20), wherein a central portion (140) of the first conductive layer (100) is connected to the feed terminal (3), wherein the first conductive layer (100) has a shape with a plurality of arms extending radially from the central portion (140), wherein the plurality of arms (110, 120, 130) is connected in its distal portion (111, 121, 131) with the ground layer (300); a second conductive layer (200) arranged on a second side of the second substrate layer (20, 20?), wherein the layers (10, 20, 100, 200, 300) are realised with a multilayer circuit board.

Abstract: A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions.

Abstract: A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.

Abstract: A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface.

Abstract: A sensor arrangement comprises a communication device and a sensor element. The sensor element is configured to record a property and provide a sensor signal that represents the property. The sensor arrangement comprises a security element configured to provide a secret. The sensor arrangement is configured to link the sensor signal to the secret to obtain a linked sensor signal, transmit the linked sensor signal to a communication partner using the communication device, obtain a test signal from the communication partner using the communication device, and perform a check to determine whether the test signal comprises the secret.

Abstract: A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.

Abstract: A radar system includes a signal generator configured to generate an RF signal; a modulator configured to generate an RF test signal by modulating the RF signal with a test signal; a transmitting channel configured to generate an RF output signal based on the RF signal; and a receiving channel configured to receive an antenna signal and the RF test signal and down-convert a superposition of the two signals to baseband by means of a mixer in order to obtain a baseband signal. The radar system further includes an analog-to-digital converter configured to generate a digital radar signal based on the baseband signal, and a computing unit configured to filter the digital radar signal by means of a digital filter, wherein the filter characteristic of the digital filter has a pass band, a transition band, and a stop band. The test signal has a frequency in the transition band.

Abstract: An electronic chip is disclosed. In one example, the electronic chip comprises a substrate comprising a central portion and an edge portion around at least part of the central portion. An active region is arranged in the central portion. A crack guiding structure combined with a crack stop structure is provided, both being arranged in the edge portion.

Abstract: A magnetic field sensor includes a sensor and a processing circuit. The sensor is designed to generate on the basis of a varying magnetic field an oscillation signal that fluctuates around a mean value. The processing circuit is designed to generate an output signal on the basis of the oscillation signal. The processing circuit is designed, in a high-resolution mode different than a low-resolution mode, in each case to generate a mean value crossing pulse in the output signal when the oscillation signal attains the mean value, and to generate in each case a limit value crossing pulse in the output signal when the oscillation signal attains at least one limit value different than the mean value. A pulse width of at least either the mean value crossing pulse or the limit value crossing pulse is set to indicate that the magnetic field sensor is operating in the high-resolution mode.

Abstract: According to one configuration, a fabricator receives magnetic permeable material and fabricates an apparatus to include a multi-dimensional arrangement of electrically conductive paths to extend through the magnetic permeable material. Each of the electrically conductive paths is a respective inductive path.

Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between first and second terminals, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. One first diode is electrically coupled in parallel to each switching device of the first type. One second diode is electrically coupled in parallel to each switching device of the second type. The switching devices are arranged in a power semiconductor module having first and second longitudinal sides and first and second narrow sides. The first type switching devices and first diodes are arranged alternatingly in one row along the first longitudinal side. The second type switching devices and second diodes are arranged alternatingly in another row along the second longitudinal side. An axis of symmetry that extends perpendicular to the first and second narrow sides.

Abstract: A gas sensing device includes one or more chemo-resistive gas sensors; one or more heat sources, wherein the gas sensors are heated according to one or more first temperature profiles during the recovery phases and according to one or more second temperature profiles during the sense phases; a preprocessing processor for generating preprocessed signal samples; a feature extraction processor for extracting one or more feature values from the received preprocessed signal samples; and a gas concentration processor for creating a sensing result, wherein the gas concentration processor includes a classification processor for outputting a class decision value, wherein the classification processor is configured for outputting a confidence value, wherein the classification processor includes a first trained model based algorithm processor, wherein the gas concentration processor comprises a quantification processor for creating an estimation value, and wherein the quantification processor comprises a second trained m

Abstract: A sensor system may include a first magnet arranged such that a position of the first magnet corresponds to a position of a trigger element on a linear trajectory. The sensor system may include a second magnet arranged such that a position of the second magnet corresponds to a selected position of a selection element. The sensor system may include a magnetic sensor to detect a strength of a first magnetic field component, a strength of a second magnetic field component, and a strength of a third magnetic field component. The magnetic sensor may be further to determine the position of the trigger element based on the strength of the first magnetic field component and the strength of the second magnetic field component, and to determine the selected position of the selection element based on the strength of the third magnetic field component.

Abstract: A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

Abstract: A power module includes a metal frame having a first and second device attach pads, first and second semiconductor packages each having an encapsulant body, a die pad exposed at a lower surface of the encapsulant body, a plurality of leads protruding out from the encapsulant body, and a potting compound that encapsulates both of the first and second semiconductor packages and partially covers the metal frame. The first semiconductor package is mounted on the metal frame such that the die pad of the first semiconductor package faces and electrically contacts the first device attach pad. The second semiconductor package is mounted on the metal frame such that the die pad of the second semiconductor package faces and electrically contacts the second device attach pad. The plurality of leads from each of the first and second semiconductor packages are electrically accessible from outside of the potting compound.