Patents Assigned to Infineon Technologies
  • Publication number: 20220244535
    Abstract: An image projection system includes a first transmitter configured to generate first light beams; a first collimation lens configured to receive the first light beams and generate first collimated light beams to be projected onto an eye to render a first projection image perceived at a first projection plane; a second transmitter configured to generate second light beams; a second collimation lens configured to receive the second light beams and generate second collimated light beams to be projected onto the eye to render a second projection image perceived at a second projection plane; a first beam combiner configured to transmit the first and the second collimated light beams on a combined transmission path; and a scanner configured to steer the first and the second collimated light beams according to a scanning pattern to render the first projection image and the second projection image onto the eye.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Applicant: Infineon Technologies AG
    Inventor: Boris KIRILLOV
  • Publication number: 20220244322
    Abstract: The present disclosure relates to a magnetic field sensor circuit including at least one coil for measuring a magnetic field, a first stage amplifier circuit coupled to the coil and having a first transfer function with a pole at a first frequency, and a second stage amplifier circuit coupled to an output of the first stage amplifier circuit and having a second transfer function with a zero at the first frequency. In some embodiments, a temperature dependent frequency drift of the pole of the first transfer function corresponds to a temperature dependent frequency drift of the zero of the second transfer function.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 4, 2022
    Applicant: Infineon Technologies AG
    Inventors: Mario MOTZ, Qinwen FAN, Amirhossein JOUYAEIAN, Kofi MAKINWA
  • Patent number: 11404962
    Abstract: Disclosed is a power converter circuit and a method for operating the power converter circuit. The power converter circuit includes at least one converter stage and a control circuit. The at least one converter stage includes an input configured to receive an input power, an output configured to supply an output power, a first electronic switch, and a first inductor coupled to the first electronic switch. The control circuit includes a hysteresis controller configured to drive the first electronic switch based on a current measurement signal representing a current through the inductor, a first threshold signal, and a second threshold signal, and an operating point controller configured to detect an operating point of the converter stage to generate the first threshold signal and the second threshold signal based on the detected operating point.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Dominik Neumayr, Dominik Bortis, Gerald Deboy, Marc Fahlenkamp, Johann Kolar, Martin Krueger, Anthony Sanders
  • Patent number: 11405032
    Abstract: An integrated circuit that may be employed as a smart switch is described herein. In accordance with one embodiment the integrated circuit includes a power transistor coupled between a supply pin and an output pin and a current sensing circuit coupled to the power transistor and configured to generate a current sense signal indicative of a load current passing through the power transistor. The integrated circuit further comprises a monitor circuit configured to receive the current sense signal and to provide a protection signal based on the current sense signal and a threshold value, wherein the monitor circuit includes a filter that is configured to receive a filter input signal that depends on the current sense signal. The filter has a transfer characteristic with two or more time constants.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies AG
    Inventors: Mirko Bernardoni, Robert Illing
  • Patent number: 11403431
    Abstract: A cryptographic processing device for cryptographically processing data, having a memory configured to store a first operand and a second operand represented by the data to be cryptographically processed, wherein the first operand and the second operand each correspond to an indexed array of data words, and a cryptographic processor configured to determine, for cryptographically processing the data, a product of the first operand with the second operand by accumulating results of partial multiplications, each partial multiplication comprising the multiplication of a data word of the first operand with a data word of the second operand wherein the cryptographic processor is configured to perform the partial multiplications in successive blocks of partial multiplications, each block being associated with a result index range and a first operand index range and each block comprising all partial multiplications between data words of the first operand within the first operand index range with data words of the sec
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies AG
    Inventor: Erich Wenger
  • Patent number: 11402556
    Abstract: A method for manufacturing integrated IR (IR=infrared) emitter elements having an optical filter comprises back side etching through a carrier substrate, forming adhesive spacer elements on a conductive layer on the carrier substrate, placing a filter substrate having a filter carrier substrate and a filter layer on the adhesive spacer elements, fixing the adhesive spacer elements to the carrier substrate and the filter substrate by curing, pre-dicing through the filter substrate for exposing the contact pads of the structured conductive layer, and dicing through the frame structure in the carrier substrate for separating the integrated IR emitter elements having the optical filter.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 2, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Stephan Pindl, Matthias Steiert
  • Patent number: 11404359
    Abstract: An integrated circuit package that includes a leadframe and a mold compound encapsulating at least a portion of the leadframe. The mold compound includes a cavity open at a bottom surface of the mold compound that exposes a bottom surface of the leadframe. A thermally conductive and electrically insulating isolation layer is locked within the bottom cavity of the mold compound and contacts the bottom surface of the leadframe.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies AG
    Inventors: Stefan Schwab, Alexander Roth
  • Patent number: 11404262
    Abstract: A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10?2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies AG
    Inventors: Sophia Friedler, Bernhard Goller, Iris Moder, Ingo Muri
  • Patent number: 11404336
    Abstract: A method of forming a power semiconductor module includes providing a substrate of planar sheet metal, forming channels in an upper surface of the substrate that partially extend through a thickness of the substrate and define a plurality of islands in the substrate, mounting a first semiconductor die on a first one of the islands, forming a molded body of encapsulant that covers the substrate, fills the channels, and encapsulates the semiconductor die, forming a hole in the molded body and a recess in the upper surface of the substrate beneath the hole, and arranging a press-fit connector in the hole and forming a mechanical and electrical connection between an interior end of the press-fit connector and the substrate.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Wu Hu Li, Raphael Hellwig, Olaf Hohlfeld, Martin Mayer, Ivan Nikitin
  • Patent number: 11404370
    Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device comprises a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region comprises a control terminal. The first power region comprises a first power terminal. The second power region comprises a second power terminal. The isolation region is between the control region and the first power region. The short circuit structure extends from the first power region, through the isolation region, to the control region. The short circuit structure is configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 2, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Basler, Andreas Huerner, Caspar Leendertz, Dethard Peters
  • Patent number: 11404961
    Abstract: A power converter includes a switch, an ON-time controller, and a compensator. Over multiple control cycles, the ON-time controller controls an ON-time duration of a control signal driving the switch. Activation of the switch generates an output voltage that powers a dynamic load. The ON-time controller controls attributes such as a switching frequency and/or an ON-time duration of the control signal driving the switch to regulate the output voltage. A phase-locked loop in the compensator supplies the ON-time controller with adjustment signals that adjust the ON-time duration of activating the switch to maintain the switching frequency at a desired setpoint. Thus, if a transient load condition causes the ON-time controller to temporarily operate the switch to at a value other than the desired setpoint frequency, the phase-locked loop of the compensator causes the switching frequency to align with the desired switching frequency again over one or more control cycles.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Keng Chen, James R. Garrett
  • Patent number: 11404392
    Abstract: A molded semiconductor module include: a semiconductor die attached to a main surface of a metal block. The die has a metal contact pad at a side of the die facing away from the metal block. A metal terminal has a contact region attached to the metal contact pad of the die, and a distal end region that joins the contact region and is bent upward in a direction away from the metal block such that the distal end region has a free end which terminates at a further distance from the metal block than the contact region. A molding compound encapsulates the die and covers the contact region of the metal terminal. The distal end region of the metal terminal protrudes through a surface of the molding compound that faces a same direction as the side of the die with the metal contact pad.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies AG
    Inventor: Ivan Nikitin
  • Patent number: 11404535
    Abstract: A method includes forming a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier. Forming the layer stack includes forming a plurality of epitaxial layers on the carrier. Forming each of the plurality of epitaxial layers includes depositing a layer of semiconductor material, forming at least two first implantation regions of one of a first type or a second type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region of a type that is complementary to the type of the first implantation regions, the first implantation regions and the second implantation regions being arranged alternatingly.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Rolf Weis, Richard Hensch, Ahmed Mahmoud
  • Patent number: 11405026
    Abstract: Embodiments of the present disclosure provide systems and methods of reducing the EMI effect generated by such analog blocks. By varying the clock frequency in time of oscillators used by such analog blocks, the EMI energy may be spread over a wide spectrum range thereby reducing the peak energy for the main frequency. To achieve this, the oscillator frequency is directly varied using analog mechanisms. The mechanisms may be based on a synchronized method for increasing/decreasing the current that is charging/discharging the oscillator capacitor. The frequency variation may be achieved by analog control of the extra charge/discharge current.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies LLC
    Inventors: Oleg Dadashev, Yoram Betser
  • Patent number: 11404866
    Abstract: An embodiment electronic circuit includes an electronic switch comprising a load path, and a control circuit configured to drive the electronic switch. The control circuit is configured to operate in one of at least two operation modes. The at least two operation modes comprise a first operation mode and a second operation mode. The control circuit, in the second operation mode, is configured to perform a set of basic functions and, in the first operation mode, is configured to perform the set of basic functions and at least one additional function. The at least one additional function comprises generating a first protection signal based on a current-time-characteristic of a load current of the electronic switch and driving the electronic switch based on the first protection signal.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: August 2, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Robert Illing, Christian Djelassi, Markus Ladurner, David Jansson, Mario Tripolt, Bernhard Marinelli, Alexander Mayer
  • Patent number: 11405027
    Abstract: In accordance with an embodiment a circuit includes: a plurality of delay elements coupled in series, each delay element including an input node and an output node; a multiplexer having inputs coupled to the output node of each delay element of the plurality of delay elements; and a time measurement circuit including a time amplifier having an input coupled to an output of the multiplexer, and a counter coupled to an output of the time amplifier.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 2, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Stefano Bonomi, Nicolo Zilio
  • Publication number: 20220238481
    Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Applicant: Infineon Technologies AG
    Inventors: Petteri PALM, Thorsten SCHARF, Ralf WOMBACHER
  • Publication number: 20220239267
    Abstract: A gray zone prevention circuit includes: a first gain stage circuit including a first input terminal and a first output terminal, the first gain stage circuit amplifies a feedback signal received at the first input terminal and generates an amplified signal at the first output terminal; a second gain stage circuit including a terminal that is coupled to the first output terminal for receiving the amplified signal and a second output terminal, where the second gain stage circuit is configured to generate a monitored signal based on the amplified signal; a feedback circuit coupled between the second output terminal and the first input terminal and configured to convert the monitored signal into the feedback signal; and a comparator circuit including a monitoring node coupled to the first output terminal for receiving the amplified signal, wherein the comparator circuit is configured to monitor the monitored signal indirectly via the amplified signal.
    Type: Application
    Filed: January 26, 2021
    Publication date: July 28, 2022
    Applicant: Infineon Technologies AG
    Inventors: Christoph SCHROERS, Carlos Humberto GARCIA ROJAS, Elisa SANFILIPPO, Veikko SUMMA
  • Publication number: 20220238413
    Abstract: A double sided cooling module that includes a leadframe with a top Direct Copper Bonded (DCB) substrate and two or more power transistor submodules. Each one of the power transistor submodules includes a bottom DCB substrate, a spaced-apart row of first wires attached to a top metal layer of the bottom DCB substrate proximate to the first side of the top metal layer, a semiconductor die having a bottom side load path contact attached to a top surface of a die pad portion of the top metal layer, a top side control contact electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer, and an electrically conductive and thermally conductive spacer that is attached to the top side load path contact and to a bottom metal layer of the top DCB substrate. At least one of the first wires is attached to the control pad portion of the top metal layer and to a bottom metal layer of the top DCB substrate.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 28, 2022
    Applicant: Infineon Technologies AG
    Inventor: Andreas GRASSMANN
  • Publication number: 20220236123
    Abstract: A stress sensor includes a semiconductor substrate with a first transistor arrangement and a second transistor arrangement. The first transistor arrangement includes a first transistor with a first source-drain channel region and a second transistor with a second source-drain channel region. The first transistor and the second transistor are aligned relative to each other such that the current flow directions in the first and the second source-drain channel regions are opposite to each other. The second transistor arrangement includes a third transistor with a third source-drain channel region and a fourth transistor with a fourth source-drain channel region. The third transistor and the fourth transistor are aligned relative to each other such that the current flow directions in the third and the fourth source-drain channel regions are opposite to each other. The stress sensor generates a gradient-compensated output signal used to determine a mechanical stress acting on the semiconductor substrate.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 28, 2022
    Applicant: Infineon Technologies AG
    Inventor: Mario MOTZ