Abstract: An isolator includes a transmitter, a coupling module and a receiver. The transmitter drives an input of the coupling module in response to a digital signal, such that in response to a first type of digital data value in the digital signal, a signal of a first predetermined type is supplied to the input and in response to a second type of digital data value in the digital signal, a signal of a second predetermined type is supplied to the input, the signals of the first type and the second type each including an initiation signal that announces a time window during which another portion of the signals representing a digital data value of the first type or the second type will be valid. The receiver is coupled to an output of the coupling module to receive and to decode signals in correspondence to the signals provided to the input.

Abstract: A method is disclosed for fabricating a trench transistor, in which there are formed, within an epitaxial layer deposited above a substrate of a first conductivity type, a trench and, within the trench, a gate dielectric and a gate electrode and, in a body region of a second conductivity type adjoining the trench a source region of the first conductivity type, a drift region of the first conductivity type forming a drain zone being formed at the end of the junction between the substrate and the epitaxial layer by means of one or more high-energy implantations, the lower end of the trench projecting into said drift region, and to a trench transistor of this type formed as a low-voltage transistor.

Abstract: Embodiments provide an electronic device including a leadframe, a chip attached to the leadframe, and encapsulation material disposed over a portion of the leadframe. The leadframe includes a first main face opposite a second main face and a plurality of edges extending between the first and second main faces. At least one of the plurality of edges includes a first profiled element and a second profiled element different than the first profiled element. The encapsulation material is disposed over the chip and the plurality of edges of the leadframe.

Abstract: Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices.

Abstract: This disclosure relates to a voltage regulator system where duty cycle value of an input voltage is measured, where the input voltage is supplied to a regulator circuit that provides a regulated output voltage. Based on a calculated ideal duty cycle, which is derived from the measure duty cycle, a determination is made as to whether the regular circuit operational mode is to be changed to achieve greater efficiency.

Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

Abstract: Systems and methods for in-situ reflectivity degradation monitoring of optical collectors used in extreme ultraviolet (EUV) lithography processes are described. In one embodiment, a method comprises providing a semiconductor lithography tool employing an EUV source optically coupled to a collector within a vacuum chamber, the collector providing an intermediate focus area, measuring a first signal at the EUV source, measuring a second signal at the intermediate focus area, comparing the first and second signals, and monitoring a reflectivity parameter of the collector based upon the comparison. In another embodiment, a method comprises emitting a signal from a non-EUV light source optically coupled to the collector, measuring a signal reflected by the collector, and monitoring a reflectivity parameter of the collector based upon a comparison between the emitted and measured signals.

Abstract: Systems and methods for monitoring and controlling the operation of extreme ultraviolet (EUV) sources used in semiconductor fabrication are disclosed. A method comprises providing a semiconductor fabrication apparatus having a light source that emits in-band and out-of-band radiation, taking a first out-of-band radiation measurement, taking a second out-of-band radiation measurement, and controlling the in-band radiation of the light source, at least in part, based upon a comparison of the first and second out-of-band measurements. An apparatus comprises a detector operable to detect out-of-band EUV radiation emitted by an EUV plasma source, a spectrometer coupled to the electromagnetic detector and operable to measure at least one out-of-band radiation parameter based upon the detected out-of-band EUV radiation, and a controller coupled to the spectrometer and operable to monitor and control the operation of the EUV plasma source based upon the out-of-band measurements.

Abstract: A method and system of a GPS system controlling a voltage of an input signal to an oscillator, the oscillator producing a clock reference signal to the GPS system and a modem system, such that a frequency of the clock reference signal is altered to synchronize the modem system with a corresponding network while the GPS system remains in a locked state.

Abstract: This disclosure relates to a phase locked loop and a frequency locked loop.

Abstract: Multiple modules are connected to a signal output module via first and second busses. Different commands may be transmitted on the two busses. Both busses may be hierarchically constructed so that all units are connected one after the other in a chain like manner on the busses. The modules cooperate to transition an output signal between different duty cycles and activate and deactivate responsive to timer comparisons.

Abstract: A method is proposed for signal processing with predistortion. An amplifier circuit is provided for this purpose, whose operating states are characterized by at least one characteristic variable. A digital modulation signal having two components (R, ?), as well as a power word (LS), derived from the first component (R), are produced, and an operating state of the at least one amplifier circuit is then determined by recording of the characteristic variable. The power word (LS) is compared with the reference value and used to decide whether to predistort the first and/or the second component. A table with various predistortion coefficients is selected from at least two tables, depending on the operating state of the amplifier circuit. One predistortion coefficient is then determined from the selected table with the produced power word (LS) and the first component (R), and the predistortion coefficient is used for predistortion.

Abstract: A low impedance coupling to bias voltage dissipates abnormal charge levels within a microphone in response to a shock event such as dropping or bumping. High impedance coupling to bias voltage is thereafter restored.

Abstract: The voltage controlled oscillator (VCO) circuit comprises a tank circuit, a first tuning section comprising first capacitor elements wherein each one of the first capacitor elements is individually utilizable for the tank circuit, and a second tuning section comprising second capacitor elements wherein each one of the second capacitor elements is individually utilizable for the tank circuit and the capacitance of each one of the second capacitor elements is continuously adjustable in a predetermined capacitance range in dependence on a tuning voltage.

Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.

Abstract: A circuit arrangement for transferring electrical charge between accumulators of an accumulator arrangement includes a number of first series circuits, each connecting in parallel to one of the accumulators, and each comprising a switching element and an inductive storage element connected in series to the load path of the switching element. The circuit arrangement also includes a further series circuit connected in parallel to the accumulator arrangement and comprising a further switching element having a load path and a control terminal, and a further inductive element connected in series to the load path, the further inductive element being inductively coupled to the inductive elements of the first series circuits. The circuit arrangement also includes a control circuit comprising a number of first control outputs connected to the control terminals of the switching elements of the first series circuits, and a further control output connected to the control terminal of the further switching element.

Abstract: In order to generate a control signal for adjusting a driver stage with an adjustable output impedance, an impedance signal is generated for a measure of the output impedance of the driver stage. The difference between the impedance signal and a reference signal is calculated, and passed to a sigma-delta modulator to generate a digital bitstream signal. The control signal is then generated depending on the bitstream signal, where the frequencies of the two signal states in the bitstream signal are evaluated by means of digital counters. Depending on the difference of the determined frequencies of the two signal states, a counter is increased or reduced, and the control signal is generated depending on the count of the counter. The impedance signal may be generated by a replica circuit of a pull-up region or a pull-down region of the driver stage to be adjusted.

Abstract: A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is read with a first bit length from a first bit field in the first memory unit starting at a first start point. The bit segment that has been read is stored in the first bit field in the second memory unit starting at a second start point. The first or the second start points is updated by a predetermined value and the updated start point is stored for subsequent method steps.

Abstract: A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.

Abstract: A circuit arrangement having a voltage regulator, which is designed to generate a regulated operating voltage, and a voltage monitoring unit, which is designed to monitor the regulated operating voltage for deviations from desired values. The voltage monitoring unit has a first detector, which is designed to cause an alarm signal to be generated when the first detector detects that the regulated operating voltage is outside a first voltage interval, and a second detector, which is designed to cause an initiator to initiate countermeasures which influence the regulated operating voltage when the second detector detects that the regulated operating voltage is outside a second voltage interval, which is inside the first voltage interval.