Abstract: A device for forming a housing for a power semiconductor module arrangement includes a mold. The mold includes a first cavity including a plurality of first openings and a second opening, the second opening being coupled to a runner system, wherein the runner system is configured to inject a mold material into the first cavity through the second opening. The device further includes a plurality of sleeves or hollow bushings, wherein a first end of each of the plurality of sleeves or hollow bushings is arranged in one of the first openings, and wherein a second end of each of the plurality of sleeves or hollow bushings extends to the outside of the mold, a heating element configured to heat the mold, and a cooling element configured to cool the plurality of sleeves or hollow bushings.

Abstract: A dual active bridge circuit includes a primary side circuit including first high-side transistor and a first low-side transistor electrically coupled at a first node, and an energy transfer inductor coupled to the first node and configured to provide an inductor current based on a voltage differential across the energy transfer inductor. A secondary side circuit includes a second high-side transistor and a second low-side transistor electrically coupled at a second node. A transformer is configured to transfer energy from the primary side circuit to the secondary side circuit based on the inductor current. A controller is configured to drive each of the transistors between respective switching states with a same duty cycle to control the voltage differential across the energy transfer inductor. The same duty cycle is less than 50% such that all of the transistors are simultaneously off for a predetermined interval.

Abstract: An isolated power converter includes: a transformer having primary winding and first and second auxiliary windings on the primary side; a converter stage configured to convert a DC input for driving the primary winding and having a resonant capacitor electrically connected to the primary winding; a controller configured to control switching of the converter stage; and a voltage supply circuit configured to select a first voltage as a supply voltage for the controller if a voltage proportional to a secondary side voltage of the transformer is at a first level or select a second voltage as the supply voltage if the voltage proportional to the secondary side voltage is at a second level greater than the first level. The first voltage corresponds to a summation of voltages across the first auxiliary winding and the resonant capacitor. The second voltage corresponds to a voltage across the second auxiliary winding.

Abstract: A method for operating a power converter and a control circuit are disclosed. The method includes, in a power converter including an input, a converter stage, a first switch connected between the input and the converter stage, a second switch connected between input nodes of the converter stage, and an output capacitor connected between output nodes of the converter stage: detecting an operating state of the power converter; and operating the power converter in a first operating mode when the power converter is in a first operating state. Operating the power converter in the first operating mode includes regulating an input current received at the input by a switched-mode operation of the first and second electronic switches.

Abstract: A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.

Abstract: An encapsulant for an electronic package is disclosed. In one example, the encapsulant comprises an electrically insulating matrix material, and a porous colorant in the matrix material.

Abstract: In some examples, a method of operating a circuit is described. The method may include performing a circuit function and estimating a probability of failure of the circuit based on one or more stress origination metrics, one or more stress victim events, and one or more initial state conditions.

Abstract: A semiconductor device includes: a drift region of a first conductivity type in a semiconductor body having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; and trenches extending into the semiconductor body from the first main surface and patterning the semiconductor body into mesas. The trenches include: a first trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; a second trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; and a third trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes. Additional semiconductor device embodiments are described herein.

Abstract: A circuit includes one or more datastores configured to store a result register and a readout counter value and logic circuitry coupled to the one or more datastores. The logic circuitry is configured to cause, for a cycle of a plurality of cycles of a periodic signal, one or more analog-to-digital converters (ADCs) to store data to the result register and modify the readout counter value in response to the one or more ADCs storing the data to the result register for the cycle. In response to a read request for the data at the result register for the cycle, the logic circuitry is configured to output the data stored by the result register, output the readout counter value for the cycle, and, after the output of the readout counter value, set the readout counter value to a predetermined value.

Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface and at least one transistor device structure, a source pad and a gate pad arranged on the first major surface, a drain pad and at least one further contact pad coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.

Abstract: An apparatus comprises a power module housing. The power module housing includes a conductive substrate and a circuit board positioned overlying the conductive substrate. A gate driver is mounted to the circuit board. A power device is mounted to the conductive substrate and is controlled by the gate driver. The power module housing includes an insulation material electrically insulating the conductive substrate from the circuit board. A monitoring component is mounted to at least the conductive substrate and is operatively coupled to the gate driver and the power device.

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Abstract: In an embodiment, a method includes: receiving raw data from a millimeter-wave radar sensor; generating a first radar-Doppler image based on the raw data; generating a first radar point cloud based on the first radar-Doppler image; using a graph encoder to generate a first graph representation vector indicative of one or more relationships between two or more parts of the target based on the first radar point cloud; generating a first cadence velocity diagram indicative of a periodicity of movement of one or more parts of the target based on the first radar-Doppler image; and classifying an activity of a target based on the first graph representation vector and the first cadence velocity diagram.

Abstract: A method of forming a semiconductor package includes producing a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, providing a first load terminal on a first surface of the first semiconductor die and a second load terminal on a second surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die; providing a liner of dielectric material on the first semiconductor die; embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.

Abstract: Error correction is proposed in which a syndrome calculation is carried out in a code domain of a second code and an efficient error correction algorithm is carried out in a code domain of a first code.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.

Abstract: A module includes: an electrically insulative housing; a driver circuit enclosed in the housing and configured to drive a control terminal of a power switch; a wireless communication circuit enclosed in the housing and configured to receive, through the housing, wireless control information transmitted to the module; and a wireless energy receiver enclosed in the housing and configured to receive, through the housing, energy wirelessly transmitted to the module, and to supply power to the driver circuit. The driver circuit is configured to drive the control terminal of the power switch based on the wireless control information received by the wireless communication circuit. A power electronic assembly that incorporates one or more of the modules and a corresponding power conversion control circuit are also described.

Abstract: A Hall sensor is disclosed. The Hall sensor comprises a first Hall element, configured to detect a component of a magnetic field in a first direction a using a sensitive area of the first Hall element. The Hall sensor further comprises a second Hall element, configured to detect a component of the magnetic field in a second direction b using a sensitive area of the second Hall element. The Hall sensor further comprises a conductor track, configured to generate a calibration magnetic field. The calibration magnetic field has a significant component on the sensitive area of the first Hall element in the second direction b. The calibration magnetic field further has a significant component on the sensitive area of the second Hall element in the first direction a.