Abstract: A memory device is provided. The memory device comprises at least one non-volatile memory cell, a write circuit configured to write to the at least one memory cell, and a read circuit configured to read from the at least one memory cell, wherein the memory device is configured to be operable in a test operating mode, in which at least one test path can be tested, and wherein the test path comprises at least a portion of the write circuit and at least a portion of the read circuit, and bypasses the at least one memory cell.

Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.

Abstract: A method of voltage regulation using a full bridge LLC converter includes: selecting a control mode for the full bridge LLC converter based on a nominal output voltage for the full bridge LLC converter, including selecting a first control mode if the nominal output voltage is a first voltage and selecting a second control mode if the nominal output voltage is a second voltage less than the first voltage; in the first control mode, operating the full bridge LLC converter as a full bridge under frequency control; and in the second control mode, operating a first half bridge of the full bridge LLC converter under frequency control and operating a second half bridge of the full bridge LLC converter under duty cycle control with valley switching.

Abstract: A semiconductor device comprising a carrier, a semiconductor die disposed on the carrier and comprising a first contact pad on a first main face remote from the carrier, and a clip. The clip comprises a horizontal portion, a vertical portion, and a bent-back portion connected with the carrier.

Abstract: Disclosed is an electronic circuit. The electronic circuit includes a first transistor device, a second transistor device, and a third transistor device, each having a control node and a load path. The electronic circuit further includes a drive circuit. The load paths of the first and second transistor devices are connected in parallel, the load path of the third transistor device is connected in series with the load paths of the first and second transistor devices, and the first transistor device and the second transistor device are integrated in a common semiconductor body. The drive circuit is configured, based on a control signal, to successively switch on the first transistor device and the second transistor device, so that the second transistor device is switched on when the first transistor device is in an on-state.

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

Abstract: The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material that at least partly fills the insulation layer groove. Both the insulation layer groove and the tungsten material extend into the semiconductor body.

Abstract: A timer circuit including a ramp voltage generator configured to generate a ramp voltage, a comparator coupled on its input side to the ramp voltage generator to receive the ramp voltage and configured to compare the ramp voltage with a switching threshold, and a voltage pulse generating circuit configured to generate a reset signal as a response to a received output signal of the comparator, wherein the reset signal has a shorter time duration than an intrinsic reset time duration of the comparator.

Abstract: A package is disclosed. In one example, the package comprises an electronic component having a first main surface with an electrically conductive first pad. The first pad has an open notch, and a spacer body mounted on the first pad and bridging at least part of the open notch.

Abstract: A device has a receiver designed to receive a data packet from a communication partner, a data processor to process the data packet in order to obtain a secret value, a transmitter designed to transmit a transmit message having information based on the secret value to the communication partner, and an authentication device designed to receive a challenge message and to use the secret value to create a response message, wherein the transmitter is designed to create the transmit message to include the response message.

Abstract: An electronic device and method is disclosed. In one example, the electronic device includes a solderable surface and at least one surface opening arranged in the solderable surface. The electronic device further includes an encapsulation material, encapsulating at least one electronic component of the electronic device, and at least one vent opening arranged in an area of the surface opening and extending through the encapsulation material.

Abstract: An ultrasonic transducer includes at least one ultrasonic transducer element, a semiconductor chip that includes the ultrasonic transducer element, and a housing. The semiconductor chip is arranged in the housing. The semiconductor chip is embedded in a dimensionally stable encapsulation, wherein a contact surface of the dimensionally stable encapsulation is configured for acoustically coupling the ultrasonic transducer to a casing. Additionally, an ultrasonic transducer system and a method for fitting the ultrasonic transducer or ultrasonic transducer system are provided.

Abstract: A gas sensor comprises a membrane, a first plate arranged on a first side of the membrane and having through openings for the passage of a gas, a second plate arranged on a second side of the membrane, the second side being situated opposite the first side, and an electronic circuit, which is connected to the membrane, the first plate and the second plate and causes the membrane to emit ultrasonic radiation, and which is configured to determine a resonant frequency of the ultrasonic radiation.

Abstract: A sensor module may include a back-bias magnet with a magnetization in a first direction. The sensor module may include a sensor chip including a first set of tunnel magnetoresistive (TMR) sensing elements. The sensor chip may be configured to determine a characteristic of a first magnetic field component using the first set of TMR sensing elements, and to generate a sensor signal based at least in part on the characteristic of the first magnetic field component. A value of the sensor signal may correspond to a linear position of a ferromagnetic object.

Abstract: A fabrication method of a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride-oxide (ONO) stack over a substrate in an in-situ atomic layer deposition (ALD) tool or chamber. Radical oxidation or oxide deposition process steps are performed to form tunnel dielectric layer overlying the substrate. Silicon nitride deposition process steps are also performed to form a multi-layer charge trapping (CT) layer in which at least some of the process parameters of silicon nitride deposition process steps are adjusted when forming the first and second CT sub-layers of the multi-layer CT layer. Subsequently, radical oxidation or oxide deposition process steps are performed in the ALD tool to form a blocking dielectric layer overlying the multi-layer CT layer.

Abstract: A package configured as power stage is disclosed. In one example, the package includes a first transistor chip and a second transistor chip being interconnected to form a half bridge, a driver chip configured for driving the first transistor chip and the second transistor chip, and an encapsulant at least partially encapsulating the first transistor chip, the second transistor chip. The driver chip, wherein the driver chip comprises electrically conductive driver pads, at least one of which being arranged on each of both opposing main surfaces of the driver chip, and comprises at least one electrically conductive driver through connection extending through the driver chip between said opposing main surfaces.

Abstract: An analog-to-digital converter is provided which is configured to output an n-bit signal in response to an analog input signal. n is greater than 1. The converter comprises n comparators, where each comparator is configured to output one bit of the n-bit signal and comprising a first input and a second input. A first comparator is configured to receive the analog input signal at its first input and a reference value at its second input and to output the first, most significant bit of the n-bit signal. For the remaining comparators, an i-th comparator, i=2 . . . n, is configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device. The i-th input device is configured to selectively provide one of 2i?1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal.

Abstract: A circuit may be used as an intelligent semiconductor switch. The circuit includes a high-side power transistor having a load current path coupled between a supply node and an output node, which is configured to provide, during operation, a load current to a load. The circuit further includes a gate driver circuit coupled to a control electrode of the power transistor, and a first stage of an overcurrent protection circuit coupled to the control electrode of the power transistor and configured to drive the control electrode such that a voltage drop across the load current path of the power transistor increases upon detection that the load current has reached a first threshold value. A second stage of the overcurrent protection circuit is coupled to the control electrode of the power transistor and configured to drive the control electrode.

Abstract: A power semiconductor device includes a semiconductor body having a front side surface, and a first passivation layer arranged above the front side surface. The first passivation layer is a polycrystalline diamond layer.

Abstract: A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.