Patents Assigned to Infineon Technologies
  • Patent number: 12340649
    Abstract: A consumable component apparatus including a receptacle region for receiving configured to receive a substance or material which is consumed under the control of a consumer device, an authentication circuit configured to authenticate the consumer device, and a switch coupled to the authentication circuit. The authentication circuit is configured to control the switch in such a way that the consumable component apparatus is activatable only if the consumer device is authenticated by means of the authentication circuit, and that the consumable component apparatus is deactivated if the consumer device is not authenticated by means of the authentication circuit.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies AG
    Inventors: Peter Laackmann, Markus Gail
  • Patent number: 12341012
    Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Gerald Rescher, Michael Stadtmueller
  • Patent number: 12341432
    Abstract: A method of voltage regulation using a full bridge LLC converter includes: selecting a control mode for the full bridge LLC converter based on a nominal output voltage for the full bridge LLC converter, including selecting a first control mode if the nominal output voltage is a first voltage and selecting a second control mode if the nominal output voltage is a second voltage less than the first voltage; in the first control mode, operating the full bridge LLC converter as a full bridge under frequency control; and in the second control mode, operating a first half bridge of the full bridge LLC converter under frequency control and operating a second half bridge of the full bridge LLC converter under duty cycle control with valley switching.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies Austria AG
    Inventor: Tae Yong Kim
  • Publication number: 20250201754
    Abstract: A semiconductor device comprising a carrier, a semiconductor die disposed on the carrier and comprising a first contact pad on a first main face remote from the carrier, and a clip. The clip comprises a horizontal portion, a vertical portion, and a bent-back portion connected with the carrier.
    Type: Application
    Filed: December 4, 2024
    Publication date: June 19, 2025
    Applicant: Infineon Technologies AG
    Inventors: Joon Shyan TAN, Thai Kee GAN, Lee Shuang WANG, Azlina KASSIM, Hui Wen GOH, Mei Fen HIEW, Sin Fah YAP
  • Publication number: 20250199697
    Abstract: Systems, methods, and devices provide management of power domains. Methods include activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, and performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain. Methods further include activating a second power domain of the memory controller based on a timing determined by the sequence of operations, and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 19, 2025
    Applicant: Infineon Technologies LLC
    Inventors: Itzic Cohen, Yair Sofer, Guy Levi, Eran Geyari
  • Patent number: 12330243
    Abstract: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin. Methods of forming the layer structure, a chip package and a chip arrangement are also described.
    Type: Grant
    Filed: June 21, 2024
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Alexander Heinrich, Alexander Roth, Catharina Wille
  • Patent number: 12334825
    Abstract: Disclosed is an electronic circuit. The electronic circuit includes a first transistor device, a second transistor device, and a third transistor device, each having a control node and a load path. The electronic circuit further includes a drive circuit. The load paths of the first and second transistor devices are connected in parallel, the load path of the third transistor device is connected in series with the load paths of the first and second transistor devices, and the first transistor device and the second transistor device are integrated in a common semiconductor body. The drive circuit is configured, based on a control signal, to successively switch on the first transistor device and the second transistor device, so that the second transistor device is switched on when the first transistor device is in an on-state.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Nöbauer
  • Patent number: 12334414
    Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
  • Patent number: 12336255
    Abstract: The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material that at least partly fills the insulation layer groove. Both the insulation layer groove and the tungsten material extend into the semiconductor body.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Christof Altstätter, Ingmar Neumann
  • Patent number: 12334822
    Abstract: A timer circuit including a ramp voltage generator configured to generate a ramp voltage, a comparator coupled on its input side to the ramp voltage generator to receive the ramp voltage and configured to compare the ramp voltage with a switching threshold, and a voltage pulse generating circuit configured to generate a reset signal as a response to a received output signal of the comparator, wherein the reset signal has a shorter time duration than an intrinsic reset time duration of the comparator.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventor: Julia Richter
  • Patent number: 12334458
    Abstract: A package is disclosed. In one example, the package comprises an electronic component having a first main surface with an electrically conductive first pad. The first pad has an open notch, and a spacer body mounted on the first pad and bridging at least part of the open notch.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventor: Adrian Lis
  • Patent number: 12335413
    Abstract: A device has a receiver designed to receive a data packet from a communication partner, a data processor to process the data packet in order to obtain a secret value, a transmitter designed to transmit a transmit message having information based on the secret value to the communication partner, and an authentication device designed to receive a challenge message and to use the secret value to create a response message, wherein the transmitter is designed to create the transmit message to include the response message.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Thomas Poeppelmann, Armin Krieg
  • Patent number: 12332090
    Abstract: The herein disclosed innovative concept concerns a magnetic angle sensor and a method for operating the same. The sensor includes a magnetoresistive arrangement and a magnetic source being configured to be movable relative to the magnetoresistive arrangement. The magnetoresistive arrangement includes a first magnetoresistive element configured to generate a first output signal, a second magnetoresistive element configured to generate a second output signal, and a third magnetoresistive element configured to generate a third output signal. The first, second and third magnetoresistive elements are oriented relative to each other such that they form a symmetrical geometric arrangement with equal angular distances between each other.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Joo Il Park, Se Hwan Kim, Klaus Grambichler, Gernot Binder
  • Patent number: 12334405
    Abstract: An electronic device and method is disclosed. In one example, the electronic device includes a solderable surface and at least one surface opening arranged in the solderable surface. The electronic device further includes an encapsulation material, encapsulating at least one electronic component of the electronic device, and at least one vent opening arranged in an area of the surface opening and extending through the encapsulation material.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Michael Stadler, Thomas Bemmerl
  • Patent number: 12326998
    Abstract: An ultrasonic transducer includes at least one ultrasonic transducer element, a semiconductor chip that includes the ultrasonic transducer element, and a housing. The semiconductor chip is arranged in the housing. The semiconductor chip is embedded in a dimensionally stable encapsulation, wherein a contact surface of the dimensionally stable encapsulation is configured for acoustically coupling the ultrasonic transducer to a casing. Additionally, an ultrasonic transducer system and a method for fitting the ultrasonic transducer or ultrasonic transducer system are provided.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: June 10, 2025
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Matthias Eberl, Horst Theuss, Rainer Markus Schaller, Fabian Merbeler
  • Patent number: 12327727
    Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: June 10, 2025
    Assignee: Infineon Technologies AG
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Patent number: 12326422
    Abstract: A gas sensor comprises a membrane, a first plate arranged on a first side of the membrane and having through openings for the passage of a gas, a second plate arranged on a second side of the membrane, the second side being situated opposite the first side, and an electronic circuit, which is connected to the membrane, the first plate and the second plate and causes the membrane to emit ultrasonic radiation, and which is configured to determine a resonant frequency of the ultrasonic radiation.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: June 10, 2025
    Assignee: Infineon Technologies AG
    Inventors: Matthias Eberl, Christian Bretthauer
  • Patent number: 12326831
    Abstract: In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: June 10, 2025
    Assignee: Infineon Technologies AG
    Inventors: Albrecht Mayer, Patrik Eder, Kajetan Nuernberger
  • Patent number: 12326351
    Abstract: A sensor module may include a back-bias magnet with a magnetization in a first direction. The sensor module may include a sensor chip including a first set of tunnel magnetoresistive (TMR) sensing elements. The sensor chip may be configured to determine a characteristic of a first magnetic field component using the first set of TMR sensing elements, and to generate a sensor signal based at least in part on the characteristic of the first magnetic field component. A value of the sensor signal may correspond to a linear position of a ferromagnetic object.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: June 10, 2025
    Assignee: Infineon Technologies AG
    Inventors: Simon Hainz, Matthias Pohl
  • Publication number: 20250185250
    Abstract: A fabrication method of a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride-oxide (ONO) stack over a substrate in an in-situ atomic layer deposition (ALD) tool or chamber. Radical oxidation or oxide deposition process steps are performed to form tunnel dielectric layer overlying the substrate. Silicon nitride deposition process steps are also performed to form a multi-layer charge trapping (CT) layer in which at least some of the process parameters of silicon nitride deposition process steps are adjusted when forming the first and second CT sub-layers of the multi-layer CT layer. Subsequently, radical oxidation or oxide deposition process steps are performed in the ALD tool to form a blocking dielectric layer overlying the multi-layer CT layer.
    Type: Application
    Filed: February 6, 2025
    Publication date: June 5, 2025
    Applicant: Infineon Technologies LLC
    Inventors: Michael ALLEN, Krishnaswamy RAMKUMAR