Abstract: A circuit is described that includes a switch, a switchable clamping element coupled to the switch, and a driver configured to control the switch based at least in part on a driver control signal. The driver is further configured to enable or disable the switchable clamping element. The switchable clamping element is configured to clamp a voltage across the switch when the switchable clamping element is enabled by the driver and when the voltage across the switch or a current at the switch satisfies a threshold for activating the switchable clamping element.

Abstract: An optical detector includes a first set of one or more photodiodes configured to generate a first photocurrent according to a first spectral response function of an incident light, a second set of one or more photodiodes configured to generate a second photocurrent according to a second spectral response function of the incident light, and a third set of one or more photodiodes configured to generate a third photocurrent according to a third spectral response function of the incident light. The optical detector further includes a module configured to output an indication of the intensity of the incident light according to a fourth spectral response function based on each of the first photocurrent, the second photocurrent, and the third photocurrent.

Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.

Abstract: A method of forming transistors and structures thereof. A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n type dopant. The NMOS device may be doped with either an n type or a p type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.

Abstract: A method for processing an operating sequence of instructions of a program in a processor, wherein each instruction is represented by an assigned instruction code which comprises one execution step to be processed by the processor or a plurality of execution steps to be processed successively by the processor, includes determining an actual signature value assigned to a current execution step of the execution steps of the instruction code representing the instruction of the operating sequence; determining, in a manner dependent on an address value, a desired signature value assigned to the current execution step; and if the actual signature value does not correspond to the desired signature value, omitting at least one execution step directly available for execution and/or an execution step indirectly available for execution.

Abstract: A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.

Abstract: One embodiment of the present invention relates to a magnetic field sensor comprising a squat soft-magnetic body disposed on a surface of a substrate comprising a magnetic sensor array having a plurality of spatially diverse magnetic sensor elements disposed in a predetermined configuration. In the presence of an external magnetic field the squat soft-magnetic body becomes magnetized to generate a reactionary magnetic field. The plurality of magnetic sensor elements are respectively configured to measure a magnetic field value of a superposition of the external magnetic field and the reactionary magnetic field along a first axis (e.g., a z-axis), resulting in a plurality of spatially diverse measurements of the magnetic field component along the first axis. The plurality of spatially diverse measurements may be used to compute magnetic field components of the external magnetic field along a plurality of axes (e.g., x-axis, y-axis, and z-axis).

Abstract: A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate.

Abstract: A MEMS structure includes a backplate, a membrane, and an adjustable ventilation opening configured to reduce a pressure difference between a first space contacting the membrane and a second space contacting an opposite side of the membrane. The adjustable ventilation opening is passively actuated as a function of the pressure difference between the first space and the second space.

Abstract: A machine and methods for reassign the execution order of program steps of a multi-step test program is disclosed. In an embodiment a machine for evaluating an error in a software program includes a microprocessor coupled to a memory, wherein the microprocessor is programmed to evaluate the error by (a) providing program steps of the software program, (b) assigning a position number to each program step, (c) performing an evaluation run on the program steps, (d) evaluating a performance of each program step, (e) rearranging the position number of each program step based on the performance of each program step, and (f) repeating steps (c)-(e).

Abstract: Semiconductor die are assembled on a substrate by providing the semiconductor die, substrate, and an elastically deformable foil fixture preformed with one or more sunken regions having sidewalls and a bottom, and placing the semiconductor die in the one or more sunken regions so that the foil fixture is populated with a first side of the semiconductor die facing the bottom of the one or more sunken regions and a second opposing side of the semiconductor die facing away from the bottom of the one or more sunken regions. The substrate is placed adjacent the second side of the semiconductor die with a joining material interposed between the substrate and the semiconductor die. The substrate and the populated foil fixture are pressed together at an elevated temperature and pressure via first and second pressing tool members so that the substrate is attached to the second side of the semiconductor die via the joining material.

Abstract: Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame. A reconstituted wafer is formed by filling a mold compound into the openings. The mold compound is formed around the chips. Finished dies are formed within the reconstituted wafer. The finished dies are separated from the frame.

Abstract: Implementations related to systems, devices, and methods that make use of a master slave arrangement are described. In one implementation, a method of reducing overall power consumption in a master-slave system includes generating a clock signal in a master device having a first power consumption rate, transmitting the clock signal from the master device to a slave device having a second power consumption rate, the first power consumption rate is lower than the second power consumption rate, sampling data receive by the slave device, the data being provided by the master device, generating phase error information of the clock signal in the slave device, transmitting the phase error information from the slave device to the master device, and adjusting the clock signal in response to the phase error information.

Abstract: In various embodiments, a circuit arrangement is provided, including a first antenna tuned to a first frequency range, a second antenna tuned to a second frequency range being different from the first frequency range, a controller coupled to the first antenna and the second antenna, wherein the controller is configured to receive its operational power via at least one of the first antenna and the second antenna, and a deactivating structure configured to deactivate the communication of the controller via the second antenna upon reception of electromagnetic waves with the first frequency range via the first antenna.

Abstract: In accordance with an embodiment, a directional coupler includes a coupler circuit and at least one amplifier coupled between a coupler circuit isolated port and a directional coupler isolated port and/or between a coupler circuit coupled port and a directional coupler coupled port. In various embodiments, the directional coupler is disposed over and/or in a substrate.

Abstract: According to one embodiment, a processing device for multiplying a first polynomial with a second polynomial is described including a first memory storing a representation of the first polynomial, a controller configured to separate the first polynomial into parts, a second memory storing pre-determined results of the multiplications of the second polynomial with possible forms of the parts of the first polynomial, a third memory for storing the result of the multiplication, an address logic, configured to determine, for each part of the first polynomial, a start address of a memory block of the second memory based on the form of the part and the location of the part within the first polynomial and an adder configured to add, for each determined address of the memory block of the second memory, the content of the memory block of the second memory at least partially to the contents of the third memory, wherein the data element of the third memory to which the content of a data element of the memory block of th

Abstract: A method of examining a substrate is provided. The method may include: generating a temperature gradient along a surface of the substrate; detecting a heat radiation emitted from the substrate; and determining as to whether the substrate is damaged based on the detected heat radiation.

Abstract: According to various embodiments, a contact pad structure may be provided, the contact pad structure may include: a dielectric layer structure; at least one contact pad being in physical contact with the dielectric layer structure; the at least one contact pad including a metal structure and a liner structure, wherein the liner structure is disposed between the metal structure of the at least one contact pad and the dielectric layer structure, and wherein a surface of the at least one contact pad is at least partially free from the liner structure, and a contact structure including an electrically conductive material; the contact structure completely covering at least the surface being at least partially free from the liner structure of the at least one contact pad, wherein the liner structure and the contact structure form a diffusion barrier for a material of the metal structure of the at least one contact pad.

Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.

Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.