Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.
Type:
Application
Filed:
October 1, 2013
Publication date:
April 2, 2015
Applicant:
Infineon Technologies AG
Inventors:
Thomas Fischer, Carsten Ahrens, Damian Sojka, Andre Schmenn, Edward Fuergut
Abstract: In accordance with an embodiment, a voltage controlled oscillator (VCO) includes a VCO core having a plurality of transistors, a bias resistor coupled between collector terminals of the VCO core and a first supply node, and a varactor circuit coupled to emitter terminals of the VCO core. The bias resistor is configured to limit a self-bias condition of the VCO core.
Abstract: According to an exemplary aspect a transducer arrangement comprising a supporting structure; a transducer die arranged on the supporting structure; and a lid comprising a porous material connected to the supporting structure and arranged to at least partially cover the transducer die.
Abstract: A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region. The interlayer dielectric is passivated, and bond pads are provided over the interconnect wiring and electrically connected to the interconnect wiring through openings in the passivation over the active region. Additional bond pads are provided over the ancillary wiring and are electrically connected to the interconnect wiring through additional openings in the passivation over the active region.
Type:
Grant
Filed:
February 19, 2013
Date of Patent:
March 31, 2015
Assignee:
Infineon Technologies AG
Inventors:
Achim Gratz, Scott David Wallace, Tobias Jacobs
Abstract: In various embodiments, a microelectromechanical system may include a chip, a substrate, a signal generator, and a fixing structure configured to fix the chip to the substrate. The chip may be fixed in such a way that, upon an acceleration of the microelectromechanical system, the chip is moved relative to the substrate. Furthermore, a signal may be generated by the movement of the chip by means of the signal generator.
Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.
Type:
Grant
Filed:
April 26, 2013
Date of Patent:
March 31, 2015
Assignee:
Infineon Technologies AG
Inventors:
Peter Kanschat, Andre Arens, Hartmut Jasberg, Ulrich Schwarzer
Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.
Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
Type:
Grant
Filed:
August 29, 2008
Date of Patent:
March 31, 2015
Assignee:
Infineon Technologies AG
Inventors:
Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
Abstract: One or more embodiments relate to a method of making a semiconductor structure, comprising: forming a patterned metallic layer over a semiconductor substrate; forming a second layer over the patterned metallic layer; and etching the substrate.
Abstract: Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.
Abstract: Representative implementations of devices and techniques provide selectivity for imaging devices and systems. Polarization may be applied to emitted light radiation and/or received light radiation to select a desired imaging result. Using polarization, an imaging device or system can pass desired light radiation having desired information and reject unwanted or stray light radiation.
Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.
Type:
Grant
Filed:
November 26, 2012
Date of Patent:
March 31, 2015
Assignee:
Infineon Technologies AG
Inventors:
Karlheinz Mueller, Robert Gruenberger, Bernhard Winkler
Abstract: In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.
Type:
Grant
Filed:
August 15, 2013
Date of Patent:
March 31, 2015
Assignee:
Infineon Technologies AG
Inventors:
Heimo Hartlieb, Clemens Kain, Michael Hausmann
Abstract: Some embodiments of the present disclosure relate to a sensor interface module. The sensor interface module includes a comparator having a first comparator input, a second comparator input, and a comparator output. A current- or voltage-control element has a control terminal coupled to the comparator output and also has an output configured to deliver a modulated current or modulated voltage signal to an output of the sensor interface module. A first feedback path couples the output of the current- or voltage-control element to the first comparator input. A summation element has a first summation input, a second summation input, and a summation output, wherein the summation output is coupled to the second comparator input. A supply voltage module provides a supply voltage signal to the first summation input. A second feedback path couples the comparator output to the second summation input.
Abstract: A microphone and a method for calibrating a microphone are disclosed. In one embodiment the method for calibrating a microphone comprises operating a MEMS device based on a first AC bias voltage, measuring a pull-in voltage, calculating a second AC bias voltage or a DC bias voltage, and operating the MEMS device based the second AC bias voltage or the DC bias voltage.
Type:
Grant
Filed:
November 28, 2011
Date of Patent:
March 31, 2015
Assignee:
Infineon Technologies AG
Inventors:
Dirk Hammerschmidt, Michael Kropfitsch, Andreas Wiesbauer
Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.
Type:
Grant
Filed:
October 15, 2012
Date of Patent:
March 31, 2015
Assignee:
Infineon Technologies AG
Inventors:
Simon Brewerton, Simon Cottam, Frank Hellwig
Abstract: A connecting system for electrically connecting electronic devices includes an electrically conductive first connector, an electrically conductive second connector and a clip element. The first connector is insertable in the second connector. The first connector or the second connector has a first opening into which the clip element can be inserted. In the inserted state, the clip element generates a contact pressure due to which the first connector and the second connector are pressed against one another so that an electrical contact between the first connector and the second connector is safeguarded.
Abstract: In various aspects of the disclosure, a chip card module is provided. The chip card module may include a flexible substrate having a metallization on a first and second major surface, or side, thereof. An integrated circuit affixed to the second side is oriented with chip pads facing away from the substrate. Wire bonds may connect the chip pads to the metallizations.
Type:
Grant
Filed:
July 19, 2012
Date of Patent:
March 31, 2015
Assignee:
Infineon Technologies AG
Inventors:
Frank Pueschner, Jens Pohl, Juergen Hoegerl, Wolfgang Schindler
Abstract: The invention relates to an electrical or electronic system, and more specifically, to a system with a bus, and a method to transmit data, in particular error data over a bus system. According to an embodiment, a method to transmit error data over a bus system that connects a plurality of modules/components/elements of an electronic system in a chain-like structure comprises in a first phase, transmitting information regarding what kinds of errors have occurred in the system, and in a second phase, transmitting information regarding where in the system an error has occurred.