Abstract: In accordance with an embodiment of the present invention, a process tool includes a chuck configured to hold a substrate. The chuck is disposed in a chamber. The process tool further includes a shielding unit with a central opening. The shielding unit is disposed in the chamber over the chuck.

Abstract: A method for forming a thin semiconductor device is disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection.

Abstract: A contact arrangement is provided, including a contact structure and a sense structure. The sense structure may be arranged in proximity of the contact structure. The sense structure may be configured such that a correct mechanical contacting of the contact structure will not impact the sense structure and an incorrect mechanical contacting of the contact structure will impact the sense structure.

Abstract: An electronic circuit is described comprising a load, a power supply node, a first transistor coupled between the supply node and the load such that the input at a control terminal of the first transistor controls current flow from the supply node to the load through the first transistor, a current source, a second transistor coupled between the current source and the load such that the input at a control terminal of the second transistor controls current flow from the current source to the load through the second transistor, a control node coupled to the control terminal of the first transistor and the control terminal of the second transistor and a measuring circuit connected to the point of coupling between the current source and the second transistor configured to measure the difference between the current provided by the current source and the current consumed by the second transistor.

Abstract: According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries.

Abstract: According to various embodiments, an integrated circuit structure may include: an electronic circuit being arranged on a surface of a carrier, and a solid state electrolyte battery being at least partially arranged within the carrier, wherein at least a part of the solid state electrolyte battery being arranged within the carrier is overlapping with the electronic circuit along a direction parallel to the surface of the carrier.

Abstract: In various embodiments, a substrate is provided. The substrate may include: a ceramic carrier having a first side and a second side opposite the first side; a first metal layer disposed over the first side of the ceramic carrier; a second metal layer disposed over the second side of the ceramic carrier; and a cooling structure formed into or over the second metal layer.

Abstract: A method for processing a chip is provided. The method may include: providing a chip having a front side and a back side; and forming an orientation marker on the back side of the chip by forming a hole into the chip from the front side of the chip, the hole forming the orientation marker.

Abstract: According to one aspect, a method is provided for determining a state of a receiver on a transmission line. The method may comprise, for example, evaluating a first voltage arising at a circuit point between an impedance and a transmission line coupled to the impedance, wherein the impedance is coupled between a transmitter and the receiver, and determining a state of the receiver based on the first voltage. According to further aspects, various apparatuses are provided for performing this and other methods.

Abstract: A vertical Hall sensor includes a Hall effect region and a plurality of contacts formed in or on a surface of the Hall effect region. The plurality of contacts are arranged in a sequence along a path extending between a first end and a second end of the Hall effect region. The plurality of contacts includes at least four spinning current contacts and at least two supply-only contacts. The spinning current contacts are configured to alternatingly function as supply contacts and sense contacts according to a spinning current scheme. The at least four spinning current contacts are arranged along a central portion of the path. The at least two supply-only contacts are arranged on both sides of the central portion in a distributed manner and are configured to supply electrical energy to the Hall effect region according to an extension of the spinning current scheme.

Abstract: In various embodiments, a chip module may include a first chip; and a leadframe with a first leadframe area and a second leadframe area, wherein the first leadframe area is electrically insulated from the second leadframe area; wherein the first chip is arranged at least partially on the first leadframe area and at least partially on the second leadframe area.

Abstract: A power converter circuit includes input terminals configured to receive an input voltage and an input current and output terminals configured to provide an output voltage and an output current. A boost converter stage is coupled between the input terminals and the output terminals. The power converter circuit is operable to operate in one of a first operation mode, a second operation mode, and a third operation mode dependent on the output voltage. The first, second and third operation modes are mutually different. In each of the first, second and third operation modes, the input current is controlled dependent on the input voltage.

Abstract: A semiconductor device includes a leadframe with a die pad and a first lead, a semiconductor chip with a first electrode, and a contact clip with a first contact area and a second contact area. The semiconductor chip is placed over the die pad. The first contact area is placed over the first lead and the second contact area is placed over the first electrode of the semiconductor chip. A plurality of protrusions extends from each of the first and second contact areas and each of the protrusions has a height of at least 5 ?m.

Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.

Abstract: Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure may include a recessed area having features arranged to improve performance of the transistor at or near breakdown.

Abstract: An enhanced serial interface system is disclosed. The system includes a master component and a slave component. The master component is configured to operate in a standard mode and an enhanced mode for communication. The master component includes standard terminals and hybrid terminals. Only the standard terminals are used for communicating in the standard mode. The hybrid terminals and the standard terminals are used for communicating in the enhanced mode. The slave component is configured to operate in the enhanced mode and communicate with the master component.

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract: A membrane structure is provided. The membrane structure may include: a membrane; at least one hole extending into the membrane configured to receive a fluid. The membrane may include a plurality of electrodes arranged to provide one or more electric fields to control a movement of the fluid within the at least one hole.

Abstract: An NLFSR of length k, configured to output a sequence of masked values x?i=xi+mi according to a masked recurrence x?n+k=f(x?n, . . . , x?n+k?1), the NLFSR including a nonlinear feedback function configured to compute f(x?n, . . . , x?n+k?1) so as to obtain a feedback value, a correction function configured to compute (mn, . . . , nn+k?1)+mn+k+h(mn, mn+k?1, xn, . . . , xn+k?1) to obtain a correction value c, and a corrector configured to correct the feedback value {circumflex over (x)}?n+k using the correction value c to obtain a corrected feedback value which forms x?n+k.

Abstract: A vertical Hall sensor includes first and second vertical Hall effect regions in a semiconductor substrate, with first and second pluralities of contacts arranged at one side of the first or second vertical Hall effect regions, respectively. The second vertical Hall effect region is connected in series with the first vertical Hall effect region regarding a power supply. The vertical Hall sensor further includes first and second layers adjacent to the first and second vertical Hall effect regions at a side other than a side of the first or second pluralities of contacts. The first and second layers have different doping properties than the first and second vertical Hall effect regions and insulate the first and second vertical Hall effect regions from a bulk of the semiconductor substrate by at least one reverse-biased p-n junction per vertical Hall effect region during an operation of the vertical Hall sensor.