Abstract: An improved ADSL system with improved data rate is disclosed. In one embodiment, the upstream data bit rate is increased by extending the upstream transmission band. In another embodiment, the downstream data is also increased by extending the downstream transmission band.

Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. A bank may be further divided into a plurality of blocks. A cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.

Abstract: A memory array comprises memory cells of the dynamic type having a first and a second port. A cache memory is connected to the address and data paths of the first and second ports. A refresh operation is performed through one of said ports. When a refresh operation is performed through said one port, a read operation can be performed through the cache memory in parallel.

Abstract: An improved ADSL system with improved data rate is disclosed. In one embodiment, the upstream data bit rate is increased by extending the upstream transmission band. In another embodiment, the downstream data is also increased by extending the downstream transmission band.

Abstract: Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.

Abstract: A conductor with improved magnetic field per current ratio is disclosed. The conductor includes a magnetic liner lining a second surface and sides thereof. The corners of the conductor where the second surface and the sides meet are rounded. The rounded corners have been found to improve the concentration of magnetic flux in the magnetic liner.

Abstract: A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

Abstract: An interface unit for data transfer between a processor bus and an ISDN-based bus is disclosed. The ISDN-based bus is an IOM-2 bus. The interface unit enables access to all available IOM-2 slots, thereby increasing data transfer rate between the processor and IOM-2 buses.

Abstract: An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer.

Abstract: An IC having an array of memory cells that can be accessed through two different ports is described. Read/write operation is performed through one of the ports. The refresh of the memory cell is performed through the other port. In one embodiment, the other port is only used internally to the memory array.

Abstract: Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example, ?0.5 to ?1.0V. This increases the effective plateline pulse (VPLH) to VPLH+the magnitude of the negative voltage. This results in an increase in the difference between VHI and VL0 read signals, thereby increasing the sensing window.

Abstract: An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.

Abstract: Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.

Abstract: An OLED device capable of emitting multiple colors is disclosed. In one embodiment of the invention, multiple substrates are stacked upon one another, wherein the different substrates emit light of a given color. In another embodiment of the invention, these substrates are separated by spacer particles to prevent the overlying substrates from contacting the active components.

Abstract: A barrier layer protecting, for example, a ferroelectric capacitor from hydrogen is described. The barrier layer comprises aluminum oxide with barrier enhancement dopants. The barrier enhancement dopants are selected from Ti, Hf, Zr, their oxides, or a combination thereof.

Abstract: A processor assisted memory BIST to identify detective memory addresses. The processor generates the address to be tested and the BIST generates the test data used to test the memory. Data is written to an read from memory. The read data is compared with the test data. If a mismatch occurs, the BIST generates an interrupt to identify the processor. Since the processor generated the address, the defective memory address is identified. The defective memory address can subsequently be replaced with redundant memory cells.

Abstract: A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

Abstract: A redundancy unit includes first and second fuse blocks for programming the redundancy element. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before packaging and as well as after.

Abstract: A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.

Abstract: A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is disclosed. The capacitor includes upper and lower portions. The demarcation between the upper and lower portion is located between top and bottom surfaces of the capacitor dielectric layer. A dielectric layer is provided on the sidewalls of the upper portion of the capacitor to prevent shorting between the electrodes that can be caused by a conductive fence formed during processing.