Abstract: A process for fabricating integrated circuits is disclosed. In particular, the process includes rounding corners of the active regions. In one embodiment, a substrate prepared with a support region having an active area between first and second trench isolations. The top surfaces of the trench isolations extend above the surface of the substrate. First and second etch stop layers are deposited on the substrate, lining the substrate surface and trench isolations without filling the gap. The etch stop layers can be etched selective to each other and layers beneath and or above. The second etch stop layer includes horizontal and vertical portions. An etch selectively removes the vertical portions of the etch stop layer. An isotropic etch is then performed, removing exposed portions of the first etch stop layer. The second etch stop layer acts as an etch mask. The etch also creates an undercut beneath the second etch stop layer, exposing edge portions of the active area.

Abstract: Reduced degradation to capacitor properties is disclosed. A hydrogen storage layer is provided over at least a portion a top capacitor electrode. The hydrogen storage layer absorbs and stores hydrogen, preventing hydrogen from diffusing to the capacitor. The hydrogen storage layer has, for example, lanthium nitride, titanium zirconium nitride, amorphous sm—co, nanostructured carbon, or a combination thereof.

Abstract: An alignment or overlay mark with improved signal to noise ratio is disclosed. Improved signal-to-noise ratio results in greater depth of focus, thus improving the performance of the alignment mark. The alignment mark comprises a zone plate having n concentric alternating opaque and non-opaque rings. Light diffracted by either the odd or even rings are cancelled while light diffracted by the other of the odd or even rings are added.

Abstract: A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.

Abstract: A non-volatile memory cell which can be easily integrated into processes for forming DRAM cells using trench capacitors is disclosed. The non-volatile memory cell comprises a transistor formed in a trench created below the top surface of the substrate. The transistor includes a U-shaped floating gate which lines the trench. A dielectric layer surrounds the floating gate, isolating it from the trench sidewalls and bottom as well as a control gate located in the inner trench formed by the floating gate. A buried diffusion region abuts the bottom of the floating gate. First and second diffusion regions are located on first and second sides of the trench. The first diffusion region is on the surface of the substrate while the second diffusion region extends from the surface and couples to the buried diffusion region. A wordline is coupled to the control gate.

Abstract: A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.

Abstract: An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is achieved by using a strap. The use of a strap eliminates the need for additional metal layer which reduces manufacturing costs. Furthermore, sidewall spacers are used to isolate the strap from the different layers of the capacitors. The use of spacers advantageously enables the strap to be self-aligned.

Abstract: An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.

Abstract: A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

Abstract: An integrated circuit having a BIST control unit for testing a plurality of memory banks simultaneously is described. The BIST control unit is coupled to a plurality of comparator units. In one embodiment, a comparator unit is coupled to a memory bank to facilitate parallel testing.

Abstract: A fuse cell with reduced or no static power dissipation is disclosed. The fuse cell utilizes a latch to store the state of the fuse. The use of the latch avoids having a pull-up power source being coupled to ground when the fuse is uncut as with conventional fuse cells. The fuse cell employs a control circuit connected to the latch and the fuse cell. When the control circuit receives an initialization signal, it sets the latch into a first state. When the initialization signal is removed, the control circuit couples the latch to the fuse circuit. In one of the latch's two states, the voltage the latch applies across the fuse is low (or zero). Conversely, if the latch takes the other state upon being coupled to the fuse, then the control circuit detects the state of the latch and in this case decouples the fuse from the latch circuit.

Abstract: A fuse cell with reduced or no static power dissipation is disclosed. The fuse cell utilizes a latch to store the state of the fuse. The use of the latch avoids having a pull-up power source being coupled to ground when the fuse is uncut as with conventional fuse cells.

Abstract: A method and apparatus of planarizing substrates is disclosed. A planarizing web medium is prepared for planarizing substrates to reduce defect generation. The planarizing web has a planarizing region and preparing region defined thereon, wherein at least one portion of the preparing region is outside the planarizing region. The web medium is advanced to move one portion of the web out of the planarizing region and another portion into the planarizing region.

Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.

Abstract: A method of reliability testing is disclosed. A critical breakdown resistance of a device is determined. The test structure is subjected to stress conditions and electrically tested. The critical breakdown time of the test structure is recorded when the operating resistance of the test structure is equal or smaller than the critical breakdown resistance.

Abstract: An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.

Abstract: An improved memory IC whose memory cells are configured in a chain architecture is disclosed. The first diffusion regions of the cell transistors of the chain are coupled to first capacitor electrodes while the second diffusion regions are coupled to second capacitor electrodes. This ensures that the electric field applied across any of the capacitors of the chain by a plateline pulse is in the same direction. This reduces or avoids asymmetrical hysteresis curves for adjacent memory cells, thereby the improving sensing window.

Abstract: An barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier slack includes first and second barrier layers formed from, for example, Ir, Ru, Pd, Rh, or alloys thereof. The first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation (RTO) prior to formation of the second barrier layer. The RTO forms a thin oxide layer on the surface of the first barrier layer. The thin oxide layer passivates the grain boundaries of the first barrier layer as well as promoting mismatching of the grain boundaries of the first and second barrier layer.

Abstract: A software programmable fuse cell which reduces or eliminates static power consumption is disclosed. The programmable fuse cell can be operated in programmable and non-programmable operating modes. Depending on the operating mode, the fuse cell output is determined by the actual state of the fuse or which fuse state the fuse cell is simulating. To reduce static power consumption, a latch is used to store the actual or simulated fuse state.

Abstract: A magnetic memory cell is disclosed. The memory cell includes first conductor and second conductors coupled to first and second electrodes of a magnetic element. A plurality of memory cells is interconnected by first and second conductors to form a memory array or block. The second conductor is coupled to the second electrode via a conductive strap having a fuse portion. The fuse portion can be blown to sever the connection between the second conductor and magnetic element, Nitride.