Abstract: In an IC having memory cells, a write operation is performed on a word within a particular row of memory cells. The other words within the same row are refreshed during the same cycle. In another embodiment, dual port memory cells are employed to enable a second row of memory cells to be refreshed during the same cycle.

Abstract: A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.

Abstract: A memory cell which provides a diffusion path for hydrogen to the transistor is disclosed. The diffusion path is provided by forming a contact in which the upper section overlaps the lower section, thus creating a gap that serve as a hydrogen diffusion path. The hydrogen diffusion path is necessary for annealing the damage to the gate oxide.

Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.

Abstract: A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.

Abstract: A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.

Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. Such a mapping causes sequential data bytes to be stored in alternate banks. Each bank may be further divided into a plurality of blocks. By staggering or synchronizing the processors to execute the computer program such that each processor access a different block during the same cycle, the processors can access the memory simultaneously.

Abstract: An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.

Abstract: A device for holding a part comprises a retainer member provided for applying and holding the part and having a convexly spherical surface section which is received in a concavely spherical surface section of a receptacle member. To enable movement of the spherical surface sections relative to one another, the device includes an arrangement for forming a temporary friction-free air bearing between the two surface sections, which can be removed once the surfaces of the two parts have been brought into the desired alignment and engagement to fix the receptacle and retainer members in position.

Abstract: The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile memory cell which is modified to permanently retain data by using one refresh port to transmit an active low voltage signal and configuring one terminal of the storage transistor to receive either an active high or low voltage signal.

Abstract: A two transistor cell NOR architecture flash memory is provided wherein the floating gate transistor is couple between the selection transistor and an associated bit line. The flash memory is deposited within a triple well and operates according to a Fowler-Nordheim tunnel mechanism. Programming of memory cells involves tunneling of carriers through gate oxide from a channel region to a floating gate rather than tunneling from a drain or source region to the floating gate.

Abstract: The process for the direct preparation of cleaning solutions for semiconductor manufacture comprises producing the cleaning solutions directly at the site of use by mixing a gas with high-purity water, with a static mixer system being used. At least one of the gases NH3, HCl, ozone or HF is added.

Abstract: A switched-mode power supply with a switch for applying a supply voltage to a primary coil of a transformer based on the criterion of a drive signal. A pulse-width modulator has supplied a first regulating signal that is dependent on an output voltage and a first current signal that is dependent on a voltage through the primary coil for providing the drive signal. A second regulating signal that is variable in dependency on the current through the primary coil is also supplied to the pulse-width modulator in addition to the first regulating signal and first voltage signal. A method is provided for driving the switch in a switched-mode power supply.

Abstract: A circuit arrangement is provided that is suitable for determining the output power of switched-mode power supplies. A charge capacitor is charged with a constant current for the duration of the discharging time of a transformer. The voltage across the charge capacitor is integrated by a downstream integration element. The output voltage of the integration element is proportional to the mean power of the switched-mode power supply. The inventive circuit arrangement takes into consideration that the charging and discharging times of the transformer can be different for different switching frequencies of the switched-mode power supply, even when the power output of the switched-mode power supply is the same.

Abstract: A power semiconductor module includes a lead frame, at least one power semiconductor component fastened on said lead frame, a housing at least partly encapsulating said power semiconductor component, a plurality of output lines electrically conductively connected to said power semiconductor component and including load current-carrying output lines, electrically conductive connections between said at least one power semiconductor component and at least said load current-carrying output lines, and an interrupter. The interrupter irreversibly interrupts at least said load current-carrying output lines and/or said electrically conductive connections and at least said load current-carrying output lines, if the temperature of said power semiconductor component exceeds a predetermined temperature threshold. The interrupter is formed of a material having a volume-expanding and/or an oxidizing and/or an explosive characteristic with an increasing temperature.

Abstract: A drive circuit for a non-volatile semiconductor storage configuration. The drive circuit having a level converter circuit which applies an output value and a complementary output value complementary to the output value to a bit line and/or a word line of the semiconductor storage configuration. The drive circuit also has a latch circuit that temporarily stores the data to be stored in the semiconductor storage configuration, and lies between an input circuit and the level converter circuit.