Abstract: The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile memory cell which is modified to permanently retain data by using one refresh port to transmit an active low voltage signal and configuring one terminal of the storage transistor to receive either an active high or low voltage signal.

Abstract: A memory chain with capacitors having different capacitances, depending on the location of the memory cell within the chain, is described. Varying the capacitances of the capacitors advantageously enables an effective capacitance for all memory cells within the chain to be about the same.

Abstract: An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.

Abstract: An IC with a memory array having a series architecture is disclosed. The memory cells of the series group are arranged in pairs in which the capacitors of a memory cell pair are stacked one on top of the other. This advantageously allows for larger capacitor arrays without increasing the chip size.

Abstract: A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh operation is described. The refresh operation is allocated to the port that is not externally accessed. When accesses through both ports are requested, a wait cycle for one of the access requests is inserted until the refresh is terminated.

Abstract: The present invention describes an information recorder which is integrated into an IC, such as ferroelectric RAM device. The recorder counts desired events, such as memory accesses or length of time powered up and stores such information in a latch. The information can be retrieved from the latch to assist in failure analysis and device characterization.

Abstract: An integrated memory device comprises a multitude of sense amplifiers which output an amplified data signal on a data line. The data line is forced to a precharge potential when idle. A transistor connects the data line to a precharge potential. The memory device avoids the kickback effect during a data read operation.

Abstract: An improved reference voltage generation is described. In one embodiment, a memory block includes a plurality of memory cells interconnected by wordlines and bitlines. A plurality of reference cells are provided. A bitline includes a reference cell. The bitlines of the memory block are divided into groups or bitlines. The reference cells within a group are interconnected to average out the reference cell charge variation to improve the sensing window.

Abstract: An improved redundancy scheme for a memory matrix is disclosed. The memory matrix a plurality of memory cells interconnected in first and second directions. The memory cells are grouped into memory elements. A redundant memory element having a plurality of redundant memory cells is provided. The redundant memory element is segmented into R sections in the first direction, wherein R is a whole number greater to or equal to 2. By segmenting the redundant element into R sections, it can be used to repair defects in up to R different memory elements.

Abstract: In a circuit arrangement for discharging at least one circuit node, an input and at least one output connectible to the at least one circuit node are provided along with at least one controllable resistor, a capacitor and a diode. A first terminal of the controllable path of the controllable resistor is connected to the output. A second terminal of the controllable path of the controllable resistor is connected to the input. A terminal of the capacitor and a cathode of the diode are connected to a control terminal of the controllable resistor. An anode of the diode is connected to the input. The circuit arrangement requires a very small area in an integrated circuit and enables a very fast discharge of the circuit node.

Abstract: A processor for performing fast Fourier-type transform operations is described. Butterfly operations are performed on input values a prescribed number of times, a butterfly operation comprising three multiply operations and a plurality of add operations.

Abstract: A processor for performing fast Fourier-type transform operations is disclosed. At least one multiplier and a plurality of adders are provided to perform butterfly operations comprising three multiply operations and a plurality of add operations. Internal wordlengths are wider than wordlengths of input values to reduce rounding error.

Abstract: In the manufacture of integrated semiconductor structures, the problem frequently occurs that the resistance of polysilicon structures employed as interconnects must be selectively lowered. In order to reduce the resistance of a polysilicon structure, the structure is often provided with a silicide layer. However, the manufacturing problem occurs when siliconizing only specific polysilicon structures but not siliconizing others, for example those that are to be employed for resistors.

Abstract: An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.

Abstract: A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in the first region and at least one trench in the second region, and the trenches have a depth of at least 2 &mgr;m. The trenches in the first region are treated to provide first and second electrodes separated by a dielectric to form the capacitors and each trench in the second region provides an insulation which surrounds any wells in the second region.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.

Abstract: An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.

Abstract: The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and driven via word and bit lines. This memory device comprises two metallized sheets through which the bit line is led and between which the memory cell stacked capacitor is arranged.

Abstract: A capacitor with improved reliability is disclosed. The capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A contact, which is electrically coupled to the top electrode, is provided. At least a portion of the contact is offset from the capacitor. By offsetting the contact from the top electrode, the etch damage to the top electrode is reduced, thereby reducing or eliminating the need for the anneal to repair the etch damage.

Abstract: A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.