Abstract: This disclosure includes novel ways of implementing a power supply that powers a load. A main battery source produces a main battery voltage; each of multiple auxiliary battery sources in a set produces a respective auxiliary battery voltage. A controller initially sets a battery supply voltage to the main battery voltage, the main battery voltage is supplied to a power converter. The controller then monitors a magnitude of the battery supply voltage and adjusts the battery supply voltage supplied to the power converter based on a comparison of the magnitude of the battery supply voltage with respect to a threshold level. The adjusted battery supply voltage is provided from a serial connection of the main battery source and a first auxiliary battery source in the set.

Abstract: A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, and a capacitor monolithically formed in the semiconductor die, wherein a dielectric medium of the capacitor includes a first section of the barrier layer.

Abstract: A method for driving a power transistor includes comparing a measurement signal that is representative of a load current to a comparator threshold that corresponds to an overcurrent threshold; generating a first fault signal when the measurement signal exceeds the comparator threshold for a first time interval; generating a second fault signal when the measurement signal exceeds the comparator threshold for a second time interval that is greater than the first time interval; regulating a control voltage provided to the control terminal of the transistor to turn off the transistor in response to the second fault signal; and in response to the first fault signal, adjusting the control voltage to an adjusted voltage level in order to limit the load current to a reduced current level that is preconfigured to be greater than the overcurrent threshold. The adjusted voltage level is sufficient to maintain the power transistor in an on-state.

Abstract: A method for operating a power converter arrangement and a corresponding controller are disclosed. The method includes operating the power converter arrangement in a surge mode, when a DC link voltage of the power converter arrangement reaches a first voltage threshold. The power converter includes a first power converter having an input and an output; a second power converter having an input and an output; and a DC link capacitor circuit coupled to the output of the first power converter and the input of the second power converter and providing the DC link voltage. Operating the power converter arrangement in the surge mode includes: deactivating the second power converter; and operating, at least temporarily, the first power converter in a reverse mode to transfer energy from the DC link capacitor circuit to the input of the first power converter.

Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.

Abstract: A semiconductor device includes: a semiconductor substrate; a first gate trench and a second gate trench both extending from a first main surface of the semiconductor substrate into the semiconductor substrate; a semiconductor mesa delimited by the first and second gate trenches; and a field plate trench extending from the first main surface through the semiconductor mesa. The field plate trench includes a field plate separated from each sidewall and a bottom of the field plate trench by an air gap. The field plate is anchored to the semiconductor substrate at the bottom of the field plate trench by an electrically insulative material that occupies a space in a central part of the field plate, the electrically insulative material spanning the air gap to contact the semiconductor substrate at the bottom of the field plate trench. Methods of producing the semiconductor device are also described.

Abstract: In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.

Abstract: A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.

Abstract: A control circuit, a power supply including a control circuit, and a method are disclosed. The control circuit is configured to activate a second output capacitor connected in parallel with a first output capacitor of a power supply when the power supply is in a normal operating mode, and deactivate the second output capacitor when the power supply is in a standby mode.

Abstract: A transformer includes a winding configured to carry a current. The winding includes a conductor structure through which the current flows and a graphene layer arranged in direct contact with the conductor structure.

Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Abstract: A power conversion method is disclosed. The method includes operating a PFC converter configured to receive three input voltages and provide a DC link voltage between DC link nodes in one of at least two different operating modes, and operating an SR converter coupled to the PFC converter via the DC link nodes in one of at least two different operating modes dependent on an output voltage of the SR converter. Operating the SR converter includes regulating a voltage level of the DC link voltage dependent on a DC link voltage reference, and the at least two different operating modes of the SR converter include a buck mode and a series resonant mode.

Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

Abstract: An apparatus may include a regulated power converter, a control engine configured to control the regulated power converter based upon a regulation control parameter, and a parameter control system. The parameter control system may be configured to detect a transient event at an output of the regulated power converter. The parameter control system may be configured to modify, in response to the transient event, the regulation control parameter from a first value to a second value based upon a parameter modification profile. The parameter control system may be configured to modify, in response to modifying the regulation control parameter from the first value to the second value, the regulation control parameter according to a function of the parameter modification profile. The function may define a return of the regulation control parameter from the second value to the first value over a period of time.

Abstract: A method of passively braking a motor to reduce a current motor speed includes generating at least one control signal to control a first load current generated by a first half bridge circuit and a second load current generated by a second half bridge circuit. During passive braking, the method includes synchronously driving a first high-side transistor and a second high-side transistor between their respective switching states at an alternating shorting frequency such that they are simultaneously in a same switching state, and synchronously driving a first low-side transistor and a second low-side transistor between their respective switching states at the alternating shorting frequency such that they are simultaneously in a same switching state, wherein the first high-side transistor and the second high-side transistor are driven in a complementary manner to the first low-side transistor and the second low-side transistor according to a predetermined duty cycle.

Abstract: According to some embodiments, a half-bridge circuit is provided. The half-bridge circuit includes a substrate, a monolithic die over the substrate, a switch node, a high-side switch integrated with the monolithic die and coupled to the switch node, and a conductive structure including a first terminal coupled to the substrate and a second terminal coupled to the switch node.

Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

Abstract: An apparatus such as a power supply includes a controller and multiple power converter phases. The controller controls operation of the multiple power converter phases to produce an output voltage that powers a load. The multiple power converter phases are coupled in parallel to convert an input voltage into an output voltage. The controller further controls a flow of current through a series circuit path connecting multiple windings of the multiple power converter phases to operate the power supply in different modes.

Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.

Abstract: A diode is proposed. The diode includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. The diode further includes an anode region and a cathode region. The anode region is arranged between the first main surface and the cathode region. An anode pad area is electrically connected to the anode region. The diode further includes a plurality of trenches extending into the semiconductor body from the first main surface. A first group of the plurality of trenches includes a first trench electrode. A second group of the plurality of trenches includes a second trench electrode. The first trench electrode is electrically coupled to the anode pad area via an anode wiring line and the second trench electrode.