Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

Abstract: Systems, methods, and devices securely boot processors and nonvolatile memories. Methods include implementing, using a controller of a secured nonvolatile memory, a validation operation on a first portion of code stored in a first secured storage region of the secured nonvolatile memory, the validation operation comprising computing a validation value. Methods also include retrieving a second portion of code from a second secured storage region, the second portion of code comprising a pre-computed validation value, the first and second portion of code being associated with booting a processor, and implementing a comparison operation of the validation value and the pre-computed validation value. Methods further include generating, using the controller, a signal based on a result of the comparison operation, the signal being provided to the processor via an interface of the secured nonvolatile memory, and the signal enabling booting of the processor in response to a matching comparison operation.

Abstract: A fabrication method of a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride-oxide (ONO) stack over a substrate in an in-situ atomic layer deposition (ALD) tool or chamber. Radical oxidation or oxide deposition process steps are performed to form tunnel dielectric layer overlying the substrate. Silicon nitride deposition process steps are also performed to form a multi-layer charge trapping (CT) layer in which at least some of the process parameters of silicon nitride deposition process steps are adjusted when forming the first and second CT sub-layers of the multi-layer CT layer. Subsequently, radical oxidation or oxide deposition process steps are performed in the ALD tool to form a blocking dielectric layer overlying the multi-layer CT layer.

Abstract: In accordance with an embodiment, a circuit includes: a trimmable reference current generator having a temperature dependent current output node, the trimmable reference current generator including: a proportional to absolute temperature (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including a first output coupled to the temperature dependent current output node; and a reference interface circuit having an input coupled to the temperature dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.

Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

Abstract: A system and method are provided for generating Unique Digital Signatures (UDS) for semiconductor memories to improve data security. Generally, the method involves allocating a number of native memory cells in a memory device; obtaining a multibit binary entropy string (BES) using variations of threshold voltages (VT) of the allocated cells as an entropy source; and mathematically manipulating the BES to generate the UDS. Optionally, the BES can be concatenated with another multibit binary number from a second entropy source internal or external to the memory device, and the result of the concatenation mathematically manipulated to generate the UDS. In one embodiment, a reference voltage is located at a median VT for the cells, and the BES is obtained by reading the cells versus the reference, assigning those having a VT above the reference a first bit value, and the remaining cells a second bit value.

Abstract: Embodiments of the present disclosure provide a temperature sensor that may be integrated into a memory device along with a 1T1C reference voltage generator to enable the 1T1C reference voltage generator to provide a temperature dependent 1T1C reference voltage to a memory core (e.g., F-RAM memory core) of the memory device. The temperature sensor may detect a temperature of the memory core, and output this information (e.g., as a trim) for use by the 1T1C reference voltage generator in providing a temperature dependent 1T1C reference voltage. In this way, both the P-term and U-term margins of the memory core may be maintained even as a temperature of the memory core increases.

Abstract: A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n?1, and the third number is 1, the total number of resistors is 2n.

Abstract: In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.

Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

Abstract: A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.

Abstract: A method can include storing host code executable by a host device in a nonvolatile memory (NVM) device and NVM code executable by the NVM device. The NVM device can validate the integrity of the NVM code in response to predetermined conditions and generate a code integrity value for validating the NVM code. The code integrity value having a size independent of a size of the host code. An authentication code can be sent to the host device that is generated with at least the code integrity value. In response to read requests from the host device, returning at least portions of the host code for execution by the host device. Corresponding devices and systems are also disclosed.

Abstract: A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

Abstract: A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.

Abstract: A method of operation of a semiconductor device that includes the steps of coupling each of a plurality of digital inputs to a corresponding row of non-volatile memory (NVM) cells that stores an individual weight, initiating a read operation based on a digital value of a first bit of the plurality of digital inputs, accumulating along a first bit-line coupling a first array column weighted bit-line current, in which the weighted bit-line current corresponds to a product of the individual weight stored therein and the digital value of the first bit, and converting and scaling, an accumulated weighted bit-line current of the first column, into a scaled charge of the first bit in relation to a significance of the first bit.

Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.

Abstract: Systems, methods, and devices implement counters with fault tolerance and power loss protection. Systems include a non-volatile memory device that includes a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing an initiation and a completion of each erase operation performed on the first counter. Systems also include control circuitry configured to generate a count value based on a current counter value of the first counter, a current counter value of the second counter, and at least one physical parameter of the first counter.

Abstract: A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.