Abstract: Systems, methods, and devices implement counters with fault tolerance and power loss protection. Systems include a non-volatile memory device that includes a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing an initiation and a completion of each erase operation performed on the first counter. Systems also include control circuitry configured to generate a count value based on a current counter value of the first counter, a current counter value of the second counter, and at least one physical parameter of the first counter.

Abstract: A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: Memory devices and methods for operating the same are provided. Generally, the device includes an array of multibit-memory-cells, each operable to store multiple bits in separate locations of a charge-trapping layer, and control-circuitry coupled to the array. The control-circuitry is operable read 1st and 2nd bit values of each cell individually based on generated first and second sensed currents, where the first and second sensed currents correspond to charges trapped in first and second bit locations. The control-circuitry executes an algorithm based on the first and second sensed currents and determines a logic state of the cell. In one embodiment, the control-circuitry averages the sensed currents, and compares this to a reference current to determine the logic state. In another, the 2nd bit value is a complement of the 1st, and the control-circuitry compares the currents to determine the logic state without use of a reference current.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor. The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. Generally, the method includes forming a tunnel-dielectric for a memory transistor over a surface of a substrate, forming a nitride charge-trapping layer over the tunnel-dielectric, and forming a gate-dielectric for a field-effect transistor over the surface of the substrate. Forming the gate-dielectric can include performing a number of oxidation processes to form a thick gate-oxide while concurrently forming a blocking-dielectric including an oxide layer over the charge-trapping layer of the memory transistor.

Abstract: A memory device including a reference voltage (VREF) generator and method for operating the same to improve memory sensing margin, and extend operational temperature range and life of the device are disclosed. Generally, the device further includes an array of non-volatile memory cells divided into a plurality of blocks, a sensing circuit coupled to the array to receive and compare memory signals therefrom to the VREF to read data from the cells. The Local reference voltage generator is configured to provide one of a number of reference voltages to the sensing circuit based on which of the blocks is being read. The array can be divided based on row and column addresses of cells in the blocks. Where the cells include 1T1C ferroelectric random access memory (F-RAM) cells, and the reference voltages are selected based on a lowest P-term or highest U-term of the cells in the block being read.

Abstract: In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: A storage device can include at least one nonvolatile (NV) memory array that includes a first section having a first physical address range, and a second section having a second physical address range. A nonvolatile fault indication can be set to at least a fault state or a no-fault state. A memory watchdog circuit configured to set the fault indication to the fault state in response to an expiration of a predetermined watchdog period, the watchdog period being reset in response to a defer indication. An address mapping circuit can be configured to, in response to the fault indication having the no fault state, mapping input addresses to the first physical addresses range, and in response to the fault indication having the fault state, mapping the same input addresses to the second physical address range. Corresponding methods and systems are also disclosed.

Abstract: A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.

Abstract: A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

Abstract: Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.

Abstract: A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.

Abstract: A method includes using a memory address map, locating a first portion of an application in a first memory and loading a second portion of the application from a second memory. The method includes executing in place from the first memory the first portion of the application, during a first period, and by completion of the loading of the second portion of the application from the second memory. The method further includes executing the second portion of the application during a second period, wherein the first period precedes the second period.

Abstract: A DC-DC converter including voltage and slope regulation and a method of operating the same are provided. Generally, the converter includes a voltage source to supply an output, a switching-circuit coupled to the voltage sources to control a voltage on the output, and a slope-detector coupled to the switching-circuit and the output to detect a slope of a voltage transition between a first and a second voltage. When the detected slope exceeds a predetermined maximum the slope-detector sends a digital signal to the switching-circuit to intermittently pause the voltage transition to limit the slope to less than the maximum. In one embodiment, the voltage source is a charge-pump, and the switching-circuit includes a logic-gate coupled to the slope-detector to turn the charge-pump ON when the detected slope is less than the maximum, and to turn OFF the charge-pump for a time when the slope exceeds the maximum.

Abstract: A method can include, for each row of a nonvolatile memory (NVM) cell array, generating a multiply-accumulate (MAC) result for the row by applying input values on bit lines. Each MAC result comprising a summation of an analog current or voltage that is a function of each input value modified by a corresponding weight value stored by the NVM cells of the row. By operation of at least one multiplexer, one of the rows can be connected to an analog-to-digital converter (ADC) circuit to convert the analog current or voltage of the row into a digital MAC value. A storage element of each NVM cell can be configured to store a weight value that can vary between no less than three different values. Corresponding devices and systems are also disclosed.

Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.

Abstract: Systems, methods, and devices securely boot processors and nonvolatile memories. Methods include implementing, using a controller of a secured nonvolatile memory, a validation operation on a first portion of code stored in a first secured storage region of the secured nonvolatile memory, the validation operation comprising computing a validation value. Methods also include retrieving a second portion of code from a second secured storage region, the second portion of code comprising a pre-computed validation value, the first and second portion of code being associated with booting a processor, and implementing a comparison operation of the validation value and the pre-computed validation value. Methods further include generating, using the controller, a signal based on a result of the comparison operation, the signal being provided to the processor via an interface of the secured nonvolatile memory, and the signal enabling booting of the processor in response to a matching comparison operation.