Abstract: A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N×analog values corresponding to N×levels of its drain current (ID) or threshold voltage (VT) levels, representing N×weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.

Abstract: A method can include storing host code executable by a host device in a nonvolatile memory (NVM) device and NVM code executable by the NVM device. The NVM device can validate the integrity of the NVM code in response to predetermined conditions and generate a code integrity value for validating the NVM code. The code integrity value having a size independent of a size of the host code. An authentication code can be sent to the host device that is generated with at least the code integrity value. In response to read requests from the host device, returning at least portions of the host code for execution by the host device. Corresponding devices and systems are also disclosed.

Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

Abstract: A memory device including a reference voltage (VREF) generator and method for operating the same to improve memory sensing margin, and extend operational temperature range and life of the device are disclosed. Generally, the device further includes an array of non-volatile memory cells divided into a plurality of blocks, a sensing circuit coupled to the array to receive and compare memory signals therefrom to the VREF to read data from the cells. The Local reference voltage generator is configured to provide one of a number of reference voltages to the sensing circuit based on which of the blocks is being read. The array can be divided based on row and column addresses of cells in the blocks. Where the cells include 1T1C ferroelectric random access memory (F-RAM) cells, and the reference voltages are selected based on a lowest P-term or highest U-term of the cells in the block being read.

Abstract: A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

Abstract: A Universal Serial Bus controller including a Vconn switch having a current controlled architecture, and method for operating the same are provided. Generally, the Vconn switch includes first and second transistors coupled in series between a Vconn terminal and a communication channel (CC) terminal, a replica switch including a source coupled to the Vconn terminal, a replica current generator including a first input coupled to a drain of the replica switch and a second input coupled to a drain of the first transistor, and a resistance control module coupled to an output of the replica current generator and including an output coupled to a gate of the second transistor. The replica current generator is operable to match a current through the replica switch to that supplied through the first and second transistors to the CC terminal, and the resistance control module is operable to control resistance of the Vconn switch.

Abstract: Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.

Abstract: A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

Abstract: A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

Abstract: A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n?1, and the third number is 1, the total number of resistors is 2n.

Abstract: A DC-DC converter including voltage and slope regulation and a method of operating the same are provided. Generally, the converter includes a voltage source to supply an output, a switching-circuit coupled to the voltage sources to control a voltage on the output, and a slope-detector coupled to the switching-circuit and the output to detect a slope of a voltage transition between a first and a second voltage. When the detected slope exceeds a predetermined maximum the slope-detector sends a digital signal to the switching-circuit to intermittently pause the voltage transition to limit the slope to less than the maximum. In one embodiment, the voltage source is a charge-pump, and the switching-circuit includes a logic-gate coupled to the slope-detector to turn the charge-pump ON when the detected slope is less than the maximum, and to turn OFF the charge-pump for a time when the slope exceeds the maximum.

Abstract: A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.

Abstract: In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.