Abstract: A circuit includes a first half bridge including a first controllable semiconductor switch and a first diode. The first controllable semiconductor switch is coupled between a first constant supply potential and a center tap of the first half bridge. The first diode is coupled between the center tap and a constant reference potential. A second half bridge includes a second diode and a second controllable semiconductor switch. The second diode is coupled between a second constant potential higher than the first potential and a center tap of the second half bridge. The second controllable semiconductor switch is coupled between the center tap and the constant reference potential. Driver circuitry controls the conducting state of the first and the second semiconductor switch thus controlling the current flow through a field connectable between the center taps.

Abstract: Embodiments of the present invention relate to methods and circuits for brightness regulation for at least one light-emitting diode in the field of general lighting, more particularly, for incandescent lamp replacement by means of a supply voltage comprising a brightness level signal, wherein the brightness level signal contained in the supply voltage is decoded and converted into a modulation signal with a duty cycle corresponding to the brightness level signal for the purpose of driving a driver circuit for the at least one light-emitting diode.

Abstract: A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer.

Abstract: System and method for adaptively altering a power supply's dead time. A method comprises detecting a start of a dead time, detecting an ending condition of the dead time, and ending the dead time. The detecting of the ending condition is based on a first current flowing through a lower portion of the power supply or a second current flowing through a gate driver of a lower switching element in the power supply.

Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Abstract: The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.

Abstract: Test structures for semiconductor devices, methods of forming test structures, semiconductor devices, methods of manufacturing thereof, and testing methods for semiconductor devices are disclosed. In one embodiment, a test structure for a semiconductor device includes at least one first contact pad disposed in a first material layer in a scribe line region of the semiconductor device. The at least one first contact pad has a first width. The test structure also includes at least one second contact pad disposed in a second material layer proximate the at least one first contact pad in the first material layer. The at least one second contact pad has a second width that is greater than the first width.

Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.

Abstract: A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

Abstract: A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract: Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least one via.

Abstract: An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material.

Abstract: One embodiment of a semiconductor device includes a fin on a first side of a semiconductor body. The semiconductor device further includes a body region of a second conductivity type in at least a part of the fin. The semiconductor device further includes a drain extension region of a first conductivity type, a source and a drain region of the first conductivity type, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region.

Abstract: An automotive electronics system includes an electronic control unit and a trace adapter. The electronic control unit is configured to receive measurement signals and provide control signals. Additionally, the electronic control unit is configured to generate or provide trace signals by replacing original instructions in a binary image with trace instructions. The trace instructions are functionally equivalent, but trigger providing the trace signals. The trace adapter is coupled to the electronic control unit. The trace adapter is configured to obtain the trace signals from the electronic control unit.

Abstract: A method for separating a layer from a substrate. The method includes providing a plurality of trenches extending from a first main surface of the substrate into the substrate. A heat treatment of the substrate is performed such that edges of the trenches grow together at the first main surface to form a closed layer at the first main surface, wherein lower portions of the trenches form one or more cavities within the substrate. After that the closed layer is separated from the substrate along the one or more cavities.

Abstract: A threshold estimate system includes a level quantizer, a correlation mechanism, and a threshold adaptation component. The level quantizer is configured to receive an input signal and to generate a quantization signal from the input signal according to one or more threshold levels. The correlation mechanism is configured to correlate the quantization signal with reference symbols to generate an output signal. The threshold adaptation component is configured to modify the one or more threshold levels according to the output signal and the input signal.

Abstract: A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus.

Abstract: A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time.

Abstract: A two-transistor flyback converter includes a transformer having a primary side and a secondary side, a first transistor connected between an input voltage source and a first terminal of the primary side, a second transistor connected between ground and a second terminal of the primary side, and a diode directly connected between the first terminal of the primary side and ground. The first and second transistors are operable to switch on and off simultaneously and with no current return from the primary side to the input voltage source when the input voltage source is less than a reflected voltage from the secondary side.