Patents Assigned to Infineon Technologies
  • Stacked semiconductor chips with separate encapsulations
    Patent number: 8334586
    Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Soon Hock Tong, Kwai Hong Wong
  • ESD clamp adjustment
    Patent number: 8335064
    Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Soldner, Gernot Langguth, Christian Russ, Harald Gossner
  • Storage circuit with fault detection and method for operating the same
    Patent number: 8334707
    Abstract: Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies AG
    Inventor: Thomas Kuenemund
  • Multi-level pulse width modulation power amplifier method and apparatus
    Patent number: 8335250
    Abstract: A baseband signal is processed by amplifying a first pulse width modulation radio frequency signal having a first non-negligible peak-to-peak amplitude and a second non-negligible peak-to-peak amplitude larger than the first non-negligible peak-to-peak amplitude. A second pulse width modulation radio frequency signal is also amplified, the second pulse width modulation radio frequency signal having a third non-negligible peak-to-peak amplitude approximately equal to the second non-negligible peak-to-peak amplitude of the first pulse width modulation signal when the baseband signal power is at or above the second threshold level. The amplified signals are constructively combined to form a pulse width modulation radio frequency signal comprising a plurality of non-negligible peak-to-peak amplitude levels each corresponding to a different baseband signal power range.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies AG
    Inventor: Johan Sjöström
  • Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component
    Patent number: 8334583
    Abstract: A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are molded at essentially the same time to produce a plastic housing for a package in each component position. The central portion of the first support bars remains outside of the plastic housing of the two packages.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies AG
    Inventors: Jeffrey Khai Huat Low, Kean Cheong Lee
  • Field plate trench transistor and method for producing it
    Patent number: 8334564
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Runtime Compensated Oscillator
    Publication number: 20120313720
    Abstract: Disclosed is a method for generating an oscillating signal and an oscillator circuit.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Applicant: Infineon Technologies Austria AG
    Inventor: Martin Feldtkeller
  • Electronic component of VQFN design and method for producing the same
    Patent number: 8330260
    Abstract: A method for producing an electronic component of a VQFN (very thin quad flat pack no-lead) design includes the following method steps: anchoring at least one integrated circuit element on a sacrificial substrate; contact-connecting the at least one integrated circuit element to the sacrificial substrate with formation of contact-connecting points on the sacrificial substrate; forming an encapsulation on a top side of the sacrificial substrate, the at least one anchored integrated circuit element being mounted on the top side of the sacrificial substrate; removing the sacrificial substrate, thereby uncovering a portion of the contact-connecting points on the underside of the encapsulation.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Michael Bauer, Ludwig Heitzer, Christian Stuempfl
  • Integrated circuit device and method for the production thereof
    Patent number: 8330252
    Abstract: An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Reimund Engl, Thomas Behrens, Wolfgang Kuebler, Rainald Sander
  • Latch based memory device
    Patent number: 8331163
    Abstract: A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Siegmar Koeppe, Winfried Kamp, Julie Aunis
  • Transponder device and method for providing a supply voltage
    Patent number: 8330578
    Abstract: Transponder circuit arrangement having antenna connections for application of a voltage signal, a load-reduction modulation device, which is coupled to the antenna connections and is designed to modulate the applied, unmodulated voltage signal, which is at a first level, and a voltage conversion device, which is coupled to the load-reduction modulation device and is designed to provide a supply voltage, the magnitude of whose level is greater than the first level.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: December 11, 2012
    Assignees: Infineon Technologies Austria AG, Technische Universitaet Graz
    Inventors: Christian Klapf, Albert Missoni, Guenter Hofer
  • Semiconductor device including molding compound layer forms a common plane with the surface of the semiconductor chip
    Patent number: 8330273
    Abstract: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Jens Pohl, Rainer Steiner
  • Semiconductor device and method
    Patent number: 8330269
    Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Matthias Stecher, Tobias Smorodin
  • Semiconductor structure and method for making same
    Patent number: 8330274
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • Process for the simultaneous deposition of crystalline and amorphous layers with doping
    Patent number: 8329532
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schaefer, Martin Franosch, Thomas Meister, Josef Boeck
  • Stray light feedback for dose control in semiconductor lithography systems
    Patent number: 8330937
    Abstract: A lithography system with a stray light feedback system is disclosed. The stray light feedback helps control critical dimension (CD) within a stray light specification limit. A stray light dose control factor is calculated as a function of the stray light measured in the exposure tool and the sensitivity of the resist. The stray light dose control factor is used to adjust the exposure dose to achieve the desired CD. The stray light may be monitored, and if a threshold level of stray light is reached or exceeded, the use of the exposure tool may be discontinued for a particular type of semiconductor product, resist, or mask level, until the lens system is cleaned.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: December 11, 2012
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Sajan Marokkey, Wai-Kin Li, Todd C. Bailey
  • MEMORY RELIABILITY VERIFICATION TECHNIQUES
    Publication number: 20120307579
    Abstract: Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: Infineon Technologies AG
    Inventors: Peter Huber, Joel Hatsch, Karl Hofmann, Siegmar Koeppe
  • Method of Manufacturing a Semiconductor Device
    Publication number: 20120309130
    Abstract: In one embodiment a method for manufacturing a semiconductor device comprises arranging a wafer on a carrier, the wafer comprising singulated chips; bonding the singulated chips to a support wafer, and removing the carrier.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 6, 2012
    Applicant: Infineon Technologies AG
    Inventors: Tze Yang Hin, Stefan Martens, Werner Simbuerger, Helmut Wietschorke, Horst Theuss, Beng Keh See, Ulrich Krumbein
  • LATERAL TRENCH MESFET
    Publication number: 20120305932
    Abstract: A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.
    Type: Application
    Filed: June 29, 2011
    Publication date: December 6, 2012
    Applicant: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Andreas Peter Meiser
  • System and method for constructing multi-write error correcting code
    Patent number: 8327223
    Abstract: An embodiment of the invention relates to a memory device and a related method. In an embodiment, a check matrix for an error-correcting code is formed so that sets of input data bits can be written, wherein each set of input data bits generates one set of error-correcting code bits that can be written independently of each other and in an arbitrary order. An error-correcting code is thereby produced without the need to erase or copy any existing, originally written bit upon presentation of new input data.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: December 4, 2012
    Assignee: Infineon Technologies AG
    Inventor: Jan Otterstedt