Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.

Abstract: A modulator using a polynomial interpolator is described herein. In a simple circuit implementation of the modulator, coefficients of a representative polynomial are generated with interpolation filters in the polynomial interpolator. Crossing points may be identified for each sampling period by incorporating a virtual carrier waveform with the representative polynomial to generate a switching output control. Among other applications, the described modulator may be used in a Class-D amplifier. The described implementations may further confer benefits such as micro-power low voltage operation, low sampling rate, and low harmonic distortion.

Abstract: A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.

Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.

Abstract: This invention relates to a module including a semiconductor chip, at least two contact elements and an insulating material between the two contact elements. Furthermore, the invention relates to a method for production of such a module.

Abstract: A method of fabricating a power semiconductor component having a semiconductor body having at least two main surfaces includes applying a layer of a metallization on at least one of the main surfaces. The layer has a thickness of at least 15 ?m and serves as a heat sink. The method also includes producing a field stop zone in the semiconductor body by implantation of protons or helium through the layer.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: A microphone arrangement includes a housing having a sound hole, a first input audio transducer with a first sensitivity and a second input audio transducer with a second sensitivity. In this microphone arrangement, the first and the second input audio transducers are arranged in the housing, such that the first input audio transducer is directly acoustically coupled with the sound hole and the second input audio transducer is indirectly acoustically coupled with a sound hole via the first input audio transducer.

Abstract: One embodiment of the present invention relates to a vertical Hall-effect device. The device includes at least two supply terminals arranged to supply electrical energy to the first Hall-effect region; and at least one Hall signal terminal arranged to provide a first Hall signal from the first Hall-effect region. The first Hall signal is indicative of a magnetic field which is parallel to the surface of the semiconductor substrate and which acts on the first Hall-effect region. One or more of the at least two supply terminals or one or more of the at least one Hall signal terminal comprises a force contact and a sense contact.

Abstract: A mobile communications radio receiver for multiple radio network operation includes an RF unit for generating a first down-converted signal from a radio signal received from a first radio network and a second down-converted signal from a radio signal received from a second radio network. Further, the receiver includes a first receiving unit including a user data channel demodulator configured to demodulate a dedicated user data physical channel and a control channel demodulator configured to demodulate a common control data channel of the first radio network based on the first down-converted signal. Still further, the receiver includes a second receiving unit including a pilot channel demodulator configured to demodulate a pilot channel of the second radio network based on the second down-converted signal. A first data connection is configured to couple control data contained in the second down-converted signal to the control channel demodulator of the first receiving unit.

Abstract: A digital-to-analog conversion arrangement for converting a digital input signal comprises first and second digital-to-analog converters (DACs) having different signal resolutions and a digital-to-analog converter selector for selecting the first DAC or the second DAC if the digital input signal has a power in a first or a second power range, respectively. The digital-to-analog conversion arrangement further comprises an analog signal merger for merging a first analog signal and a second analog signal, the first analog signal being based on a first analog output signal of the first digital-to-analog converter and the second analog signal being based on a second analog output signal of the second analog-to-digital converter. A corresponding method for digital-to-analog conversion of a digital input signal and a computer readable digital storage medium are also described.

Abstract: A mobile communications radio receiver for multiple radio network operation includes an RF unit for generating a first down-converted signal from a radio signal received from a first radio network and a second down-converted signal from a radio signal received from a second radio network. Further, it includes a first receiver comprising a paging indicator channel demodulator for demodulating a paging indicator channel of the first radio network based on the first down-converted signal, and a second receiver including a pilot channel demodulator for demodulating a pilot channel of the second radio network based on the second down-converted signal. A first data connection is configured to couple paging information contained in the second down-converted signal to an input of the paging indicator channel demodulator of the first receiver.

Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

Abstract: A system produces devices that include a semiconductor part and a non-semiconductor part. A front end is configured to receive a semiconductor part and to process the semiconductor part. A back end is configured to receive the processed semiconductor part and to assemble the processed semiconductor part and a non-semiconductor part into a device. A transfer device is configured to automatically handle the semiconductor part in the front end and to automatically transfer the processed semiconductor part to the back end.

Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

Abstract: A test apparatus includes a test input signal generator that generates a test input signal of word width N, and terminals that connect to inputs and outputs of an electrical circuit to be tested. The electrical circuit includes N digital test inputs and M digital test outputs. The terminals for the test inputs are connected to the test input signal and an electrical circuit is driven such that it outputs at its test outputs data with a macro clock cycle T of length L as test response. A compactor includes M inputs that are connected to the terminals for the test outputs of the circuit to be tested. The compactor compacts the test response with a micro clock cycle t of length l and outputs a data word of width m, where the length L is at least twice as large as the length l.

Abstract: A DC-to-DC converter includes a switching control circuit adapted to provide a control signal having a duty cycle. A switching regulator is adapted to receive both a supply voltage having the first voltage level and the control signal. The switching regulator is further adapted to provide an output signal at the second voltage level as a function of both the supply voltage and the control signal. In addition, a current sensing circuit is adapted to provide at least one alarm signal based the duty cycle of the time-varying signal. Other systems and methods are also disclosed.

Abstract: A method is disclosed of synchronizing a first high data-rate radio transceiver and a second high data-rate radio transceiver. The first high data-rate radio transceiver is associated to a first lower data-rate radio transceiver and the second high data-rate radio transceiver is associated to a second lower data-rate radio transceiver. The method comprises time synchronizing the first and second lower data-rate radio transceivers, determining a timing information concerning operation of the first high data-rate radio transceiver relative to operation of the first lower data-rate radio transceiver, transmitting the timing information to the second lower data-rate radio transceiver, and time synchronizing the first and second high data-rate radio transceivers using the transmitted timing information.

Abstract: A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are partitioned to form packages. The pitch of the resultant leads is not limited by the pitch of the lead lands of the leadframe, so the leadframe can be of the relatively cheap generic leadframe variety, in which the pitch of the lead lands is higher than the desired pitch of the leads of the completed package. The sawing operation may further include reshaping the diepad area of the leadframe to produce heat sink fins, for improved heat dissipation. The proposed process is suitable both to produce packages including only a single integrated circuit, and also to produce multi-chip modules.