Abstract: A user equipment includes a plurality of antennas to receive downlink signals from a base station, a plurality of receiver circuits each coupled to a respective one of the plurality of antennas to process the received downlink signals, an SIR estimation unit to estimate a quality of the received downlink signals, a power loop controller to generate transmit power control commands based on the estimated quality of the received downlink signals, the transmit power control commands being directed to the base station to adjust a power of the downlink signals and a diversity controller to selectively activate and deactivate one or more of the receiver circuits depending on the estimated quality of the received downlink signals.

Abstract: A receiver includes a plurality of receive antennas configured to receive radio signals from a plurality of transmit antennas, and a plurality of sets of RAKE fingers configured to generate first signals, wherein each set of RAKE fingers is coupled to a respective one of the plurality of receive antennas. The receiver further includes a weighting factor generator configured to generate weighting factors for weighting the first signals, wherein at least one of the weighting factors is generated by using first signals that are generated by at least two of the plurality of sets of RAKE fingers and received from at least two of the plurality of transmit antennas.

Abstract: A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type.

Abstract: An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.

Abstract: A semiconductor substrate and a method for producing it is disclosed. In one embodiment, a contact region and a corresponding contact material of the semiconductor substrate are formed, in regions or completely, with a protection against oxidation.

Abstract: An embodiment of the invention relates to a temperature-sensing device and a related method. In an embodiment, the device senses a temperature with a first sensing circuit configured to assert a signal when temperature is above a first temperature threshold level, and a second sensing circuit configured to substantially disable a bias current that powers the first sensing circuit when a sensed level of temperature is below a second, lower temperature threshold level. Accordingly, the device is able to draw substantially reduced current from a power source when the sensed temperature level is less than the second threshold level. Other physical parameters such as strain or pressure may also be sensed using the same technique.

Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a first semiconductive material and at least one trench disposed in the first semiconductive material, the at least one trench having a sidewall. An insulating material layer is disposed over an upper portion of the sidewall of the at least one trench in the first semiconductive material and over a portion of a top surface of the first semiconductive material proximate the sidewall. A second semiconductive material or a conductive material is disposed within the at least one trench and at least over the insulating material layer disposed over the portion of the top surface of the first semiconductive material proximate the sidewall.

Abstract: The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.

Abstract: A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

Abstract: One embodiment provides a semiconductor wafer structure including a semiconductor wafer and a spacer layer. The semiconductor wafer includes active areas. The spacer layer is configured to provide spacing between the semiconductor dice in a stacked die package and the spacer layer is disposed on one side of the semiconductor wafer.

Abstract: One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.

Abstract: A method comprises predicting a workload required for decoding a code block using a turbo decoder and selecting a power mode of the turbo decoder, the selection of the power mode depending on the prediction of the workload.

Abstract: Some embodiments of the present disclosure relate to multiband receivers that include at least one divider unit having a divisor that is other-than-two. For example, in some embodiments the divisor is an odd integer (e.g., three). Such divisors allow oscillators for respective receiver subunits in a multi-band receiver to have frequencies that are sufficiently different from one another so as to limit cross-talk interference there between, even when the receiver subunits are concurrently receiving data on adjacent channels. To facilitate this other-than-two divisor, a phase error compensation block is often used to compensate for the effects of using the other-than-two divisor.

Abstract: An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word.

Abstract: One embodiment of the present invention relates to an adaptive filtering apparatus comprising first and second real valued adaptive filters, respectively configured to receive an adaptive filter input signal based upon a transmission signal in a transmission path. The first real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a first intermodulation noise component (e.g., an in-phase component) in a desired signal and to cancel the estimated noise. The second real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a second intermodulation noise component (e.g., a quadrature phase component) in the desired signal and to cancel the estimated noise. Accordingly, each filter operates a real valued adaptive algorithm to cancel a noise component, thereby removing complex cross terms between the components from the adaptive filtering process.

Abstract: A semiconductor component including a drift zone and a drift control zone. One embodiment provides a transistor component having a drift zone, a body zone, a source zone and a drain zone. The drift zone is arranged between the body zone and the drain zone. The body zone is arranged between the source zone and the drift zone.

Abstract: Metal particles are applied to a metal foil. A semiconductor chip is placed over the metal foil with contact elements of the semiconductor chip facing the metal particles. The metal particles are heated and the metal foil is structured after heating the metal particles.

Abstract: Disclosed is a power regulator for providing precisely regulated power to a microelectronic device such as a microprocessor. Improved power regulation is accomplished by optimizing the power efficiency of the power regulator. In particular, in a multiphase system, the number of active phases is increased or decreased to achieve optimum power efficiency. The multiphase voltage regulator adapts the operating mode to maximize efficiency as the load current demand of the load device changes by adjusting the number of active phases to maximize efficiency. The total value of current provided by the regulator and the total number of active phases is determined, the total number of active phases is compared with the number of active phases required to provide the total value of current at maximum efficiency; and the number of active phases is adjusted to provide the total value of current at maximum efficiency.

Abstract: A integrated circuit comprises a circuit part to be protected and protective lines located at least one wiring level of the integrated circuit. In addition, the integrated circuit comprises logical gates coupled to the protective lines, whereby a logic circuit is formed, and a processing unit implemented to detect a manipulation of the integrated circuit by applying test patterns to the logic circuit and verifying a logic output value of the logic circuit responsive to the test patterns.

Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.