Abstract: A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v?)) based on a coded binary word (v?). The error syndrome bit sequence (s(v?)) indicates whether the coded binary word (v?) is a code word of an error correction code (C) used for coding the coded binary word (v?). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v?)), if the error syndrome bit sequence (s(v?)) indicates that the coded binary word (v?) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)?)—caused by the test bit sequence (Ti)—of the circuit.

Abstract: Systems and methods related to a memory device are provided. The systems and methods include using at least one driver with predetermined reduced driving capability to drive at least one of the memory elements of the memory device in a reliable detection algorithm. The at least one driver has reduced driving capability compared to a driver used for standard read access. The reliable detection algorithm can include detecting failing memory elements on a respective reading current diverging from an expected or expectable reading current.

Abstract: A circuit for driving light emitting diodes (LEDs) includes a first semiconductor switch and a freewheeling device coupled between a first supply terminal that provides a supply voltage and a second supply terminal that provides a reference potential. The first semiconductor switch is responsive to a driver signal. An LED and an inductor are coupled in series between a common circuit node of the first semiconductor switch and the freewheeling device and either the first supply terminal or the second supply terminal. A current measurement circuit is coupled to the LED and provides a load current signal which represents a load current passing through the at least one LED. A first feedback circuit includes an on-off controller that receives load current signal and a reference signal.

Abstract: An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil.

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.

Abstract: A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.

Abstract: A memory includes a memory cell including a first terminal, a second terminal and a channel extending between the first terminal and the second terminal. The memory further includes an energy storage element configured to support a programming of the memory cell, the energy storage element being coupled to the first terminal, an energy supply coupled to the energy storage element, and a controller. The controller is configured to activate the energy supply and to bring the channel of the memory cell into a non-conductive state for energizing the energy storage element, and to subsequently bring the channel of the memory cell into a conductive state for programming the memory cell based on the energy stored in the energy storage element.

Abstract: An embodiment of the invention relates to a power converter including an inductor coupled in series with a power switch and a resistor coupled to a winding of the inductor. Input and output power converter voltages including an input brownout condition or an output overvoltage condition are estimated, and the output voltage may be regulated, by sensing a current in the resistor. An input current waveform can thereby be controlled to replicate substantially the input voltage waveform. The controller adjusts an on time and terminates an off time of the power switch by sensing respectively a current and a change of current in the resistor. The controller may sense a current flowing in the resistor to select a line voltage range of the input voltage to the power converter. The controller may estimate an input current to the power converter employing the current flowing in the resistor.

Abstract: One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.

Abstract: Methods for manufacturing packaged devices are disclosed. In one embodiment a method includes encapsulating a first semiconductor chip with a first encapsulant, wherein the first encapsulant includes a cavity on a first main surface, mounting an electrical component on a carrier, the electrical component being a MEMS device, and placing the carrier on the first main surface of the first encapsulant such that the electrical component is enclosed by the cavity.

Abstract: A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the second material being electrically insulating. A metal layer is placed over the second material.

Abstract: A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.

Abstract: An integrated circuit includes a substrate. A surface region of the substrate includes a contact pad region. A passivation layer stack includes at least one passivation layer. The passivation layer stack is formed over the surface region and adjacent to the contact pad region. An upper portion of the passivation layer stack is removed in, in a portion of the passivation layer stack proximate the contact pad region.

Abstract: Embodiments relate to omnipolar magnetic field switches. In one embodiment, omnipolar behavior is generated in a Hall effect switch by extracting the modulus of the electric signal generated by the Hall transducer and feeding it to a single high-precision comparator, without any sampling or additional processing steps. The modulus extraction and threshold evaluation can be done in parallel.

Abstract: According to an embodiment of a field-effect semiconductor device, the field-effect semiconductor device includes a semiconductor body and a source electrode. The semiconductor body includes a drift region, a gate region and a source region of a first semiconductor material having a first band-gap and an anode region of a second semiconductor material having a second band-gap lower than the first band-gap. The drift region is of a first conductivity type. The gate region forms a pn-junction with the drift region. The source region is of the first conductivity type and in resistive electric connection with the drift region and has a higher maximum doping concentration than the drift region. The anode region is of the second conductivity type, forms a heterojunction with the drift region and is spaced apart from the source region. The source metallization is in resistive electric connection with the source region and the anode region.

Abstract: In accordance with an embodiment, a system includes a first amplifier and a first bandpass filter having an input coupled in series with an output of the first amplifier, and an output configured to be coupled to a load. The bandpass filter has a lower input impedance at an in-band center frequency than at out-of-band frequencies, and the first amplifier is configured to receive a pulse width modulated waveform filtered according to a first transfer function that attenuates sidebands of the pulse width modulated waveform.

Abstract: Embodiments relate to indirect tire pressure monitoring systems (TPMSs) and methods that utilize anti-lock braking system (ABS) signals. In embodiments, information from the ABS Hall signal is obtained in analog form, before pulse forming. The information can be analyzed for a resonance frequency within the ABS sensor. In some embodiments, the digitized information can be modulated onto the conventional ABS wheel speed clock signal for transmission to and analysis by the indirect TPMS electronic control unit (ECU). According to embodiments, additional information about higher-order harmonics of the wheel rotation can be provided to the TPMS ECU, which can then calculate a more accurate estimation of tire pressure while reducing warning latency.