Patents Assigned to Infineon Technologies
  • System and Method for Providing Voltage Supply Protection in a Memory Device
    Publication number: 20140064011
    Abstract: The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Thomas Kern
  • CHIP CARD COMMUNICATION ARRANGEMENT AND CHIP CARD COMMUNICATION CIRCUIT
    Publication number: 20140065981
    Abstract: According to an embodiment, a chip card communication arrangement is provided comprising a matching network and a chip card communication circuit comprising at least one matching network terminal, a receiver coupled to the matching network via the at least one matching network terminal and an active transmitter coupled to the matching network via the at least one matching network terminal.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Richard Sbuell, Walter Kargl, Matthias Emsenhuber
  • CHIP CARD
    Publication number: 20140062594
    Abstract: According to an embodiment, a chip card is provided comprising a signal source configured to generate a signal to be transmitted via radio, a p-channel field effect transistor and being coupled with its source terminal to an upper supply potential and with its drain terminal to a common node; an n-channel field effect transistor and being coupled with its drain terminal to the common node and with its source terminal to a lower supply potential; an operational amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to the common node, the negative input terminal is coupled to the signal source and the output terminal is coupled to the gate terminal of the p-channel field effect transistor and to the gate terminal of the n-channel field effect transistor; and an antenna coupled to the common node.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Richard Sbuell
  • Opto-Electronic Sensor
    Publication number: 20140061677
    Abstract: Some embodiments of the present disclosure relate to an infrared (IR) opto-electronic sensor having a silicon waveguide implemented on a single silicon integrated chip. The IR sensor has a semiconductor substrate having a silicon waveguide extends along a length between a radiation input conduit and a radiation output conduit. The radiation input conduit couples radiation into the silicon waveguide, while the radiation output conduit couples radiation out from the silicon waveguide. The silicon waveguide conveys the IR radiation from the radiation input conduit to the radiation output conduit at a single mode. As the radiation is conveyed by the silicon waveguide, an evanescent field is formed that extends outward from the silicon waveguide to interact with a sample positioned between the radiation input conduit and the radiation output conduit.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Bernhard Jakoby, Ventsislav Lachiev, Thomas Grille, Peter Irsigler, Sokratis Sgouridis, Ursula Hedenig, Thomas Krotscheck Ostermann
  • Circuit Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices
    Publication number: 20140062585
    Abstract: A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: Infineon Technologies Dresden GmbH
    Inventor: Rolf Weis
  • VOLTAGE REGULATOR
    Publication number: 20140062436
    Abstract: In various embodiments a voltage regulating circuit is provided which may include a control transistor at least partially formed in an n-type substrate, and a regulating circuit including a regulating output coupled to a control region of the control transistor, wherein the regulating circuit includes at least one transistor which is formed at least one of on and in the n-type substrate.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Michael Lenz
  • INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT
    Publication number: 20140061878
    Abstract: An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Mahler, Lukas Ossowski, Khalil Hosseini, Ivan Nikitin
  • SENSOR CURRENT INTERFACE TRANSCEIVER WITH ADAPTIVE LINEARIZATION
    Publication number: 20140062582
    Abstract: Some embodiments of the present disclosure relate to a sensor interface module having a linearization module that increase a size of a linear region of a current output from a high-side current source. The disclosed sensor interface module has a reference voltage source configured to generate a reference signal. An output driver stage having a high-side current source and a low-side current source is connected in series at an output node of the sensor interface module. A closed control loop configured to receive the reference signal and to generate a digital control signal that drives the high-side current source. A linearization module configured to operate the low-side current source to approximate a nonlinearity of the high-side current source and to use the approximated nonlinearity to generate a compensation function that mitigates nonlinearities in the high side current source.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Applicant: Infineon Technologies AG
    Inventor: Dirk Hammerschmidt
  • Mismatch Error Reduction Method and System for STT MRAM
    Publication number: 20140063923
    Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Mihail Jefremow, Wolf Allers, Jan Otterstedt, Christian Peters, Thomas Kern
  • METHOD FOR PROCESSING A WAFER AND METHOD FOR DICING A WAFER
    Publication number: 20140065768
    Abstract: In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die.
    Type: Application
    Filed: September 3, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Markus Menath
  • CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE
    Publication number: 20140061669
    Abstract: A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Ralf Otremba, Bernd Roemer, Erich Griebl, Fabio Brucchi
  • Semiconductor Device with a Passivation Layer
    Publication number: 20140061733
    Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
  • Pre-Sintered Semiconductor Die Structure
    Publication number: 20140061909
    Abstract: A sintered connection is formed by pressing a semiconductor die against a substrate with a dried sintering material interposed between the substrate and the semiconductor die, the dried sintering material having sintering particles and a solvent. The substrate is heated to a temperature below a sintering temperature of the dried sintering material while the semiconductor die is pressed against the substrate to form local sinter connections between adjacent ones of the sintering particles. The local sinter connections collectively provide a stable joint that fixes the semiconductor die to the substrate prior to sintering. A sintered connection is then formed between the semiconductor die and the substrate from the dried sintering material, after the stable joint is formed.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Roland Speckels, Lars Böwer, Nicolas Heuck, Niels Oeschler
  • Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices
    Publication number: 20140062544
    Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
    Type: Application
    Filed: January 9, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Rolf Weis, Franz Hirler, Martin Feldtkeller, Gerald Deboy, Matthias Stecher, Armin Willmeroth
  • System and Method for Adjusting the Sensitivity of a Capacitive Signal Source
    Publication number: 20140064523
    Abstract: In accordance with an embodiment, a system for amplifying a signal provided by a capacitive signal source includes an impedance converter having an input node configured to be coupled to a first terminal of the capacitive signal source, and an adjustable capacitive network having a first node configured to be coupled to a second terminal of the capacitive signal source and a second node coupled to an output node of the impedance converter.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Michael Kropfitsch, Andreas Wiesbauer
  • PSEUDO RANDOM NUMBER GENERATOR AND METHOD FOR PROVIDING A PSEUDO RANDOM SEQUENCE
    Publication number: 20140067891
    Abstract: In various embodiments, a pseudo random number generator is provided. The pseudo random number generator may include: a pair of shift registers, wherein a first shift register in the pair is a linear shift register and a second shift register in the pair is a nonlinear shift register, wherein the linear shift register is configured to receive a first output sequence from the nonlinear shift register, and to take the first output sequence as a basis for providing a second output sequence; wherein the pseudo random number generator is configured to take the second output sequence as a basis for providing a pseudo random sequence.
    Type: Application
    Filed: April 5, 2013
    Publication date: March 6, 2014
    Applicant: Infineon Technologies AG
    Inventor: Infineon Technologies AG
  • METHOD FOR PROCESSING A WAFER, AND LAYER ARRANGEMENT
    Publication number: 20140061873
    Abstract: A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Hirschler, Gudrun Stranzl
  • METHOD FOR MANUFACTURING A LAYER ARRANGEMENT, AND A LAYER ARRANGEMENT
    Publication number: 20140061935
    Abstract: A method for manufacturing a layer arrangement in accordance with various embodiments may include: providing a first layer having a side; forming one or more nanoholes in the first layer that are open towards the side of the first layer; depositing a second layer over the side of the first layer.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gopalakrishnan TRICHY RENGARAJAN, Christian FACHMANN
  • Circuit Arrangement with Two Transistor Devices
    Publication number: 20140063882
    Abstract: A circuit arrangement includes a first transistor device and a second transistor device. Each transistor device includes a first load terminal, a second load terminal, a gate terminal, and a control terminal. The first load terminals are electrically connected, and the control terminals are electrically connected. A capacitive storage element is connected between the first load terminals and the control terminals.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Anton Mauder
  • METHOD FOR PRODUCING A SEMICONDUCTOR LAYER
    Publication number: 20140061863
    Abstract: A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate.
    Type: Application
    Filed: November 5, 2013
    Publication date: March 6, 2014
    Applicant: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Helmut Strack, Hans-Joerg Timme, Rainer Winkler