Abstract: A power semiconductor package comprises a leadframe comprising a first die pad, a second die pad and a plurality of external contacts. The first and second die pads are separated by a first gap. A power semiconductor die is arranged on and electrically coupled to a first side of the first die pad. A diode is arranged on and electrically coupled to a first side of the second die pad. A molded body encapsulates the power semiconductor die and the diode, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides. A second side of the first die pad is exposed from the second side of the molded body. A second side of the second die pad is completely covered by an electrically insulating material.

Abstract: A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n-1, and the third number is 1, the total number of resistors is 2n.

Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

Abstract: A device for controlling trapped ions includes a first semiconductor substrate. A second semiconductor substrate is disposed over the first semiconductor substrate. At least one ion trap is configured to trap ions in a space between the first semiconductor substrate and the second semiconductor substrate. A spacer is disposed between the first semiconductor substrate and the second semiconductor substrate, the spacer including an electrical interconnect which electrically connects a first metal layer structure of the first semiconductor substrate to a second metal layer structure of the second semiconductor substrate.

Abstract: In some implementations, an angle sensor may determine an angular position of an object based on first sensor values received from a first set of sensing elements. The first sensor values include a first x-component of a magnetic field and a first y-component of the magnetic field. The angle sensor may determine the angular position of the object based on second sensor values received from a second set of sensing elements. The second sensor values include a second x-component of the magnetic field and a second y-component of the magnetic field. The angle sensor may perform a set of safety checks, including performing an x-component check based on the first x-component and the second x-component and performing a y-component check based on the first y-component and the second y-component. The angle sensor may provide an indication of a result of the set of safety checks.

Abstract: A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions.

Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.

Abstract: A radar system includes a signal generator configured to generate an RF signal; a modulator configured to generate an RF test signal by modulating the RF signal with a test signal; a transmitting channel configured to generate an RF output signal based on the RF signal; and a receiving channel configured to receive an antenna signal and the RF test signal and down-convert a superposition of the two signals to baseband by means of a mixer in order to obtain a baseband signal. The radar system further includes an analog-to-digital converter configured to generate a digital radar signal based on the baseband signal, and a computing unit configured to filter the digital radar signal by means of a digital filter, wherein the filter characteristic of the digital filter has a pass band, a transition band, and a stop band. The test signal has a frequency in the transition band.

Abstract: A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface.

Abstract: A sensor arrangement comprises a communication device and a sensor element. The sensor element is configured to record a property and provide a sensor signal that represents the property. The sensor arrangement comprises a security element configured to provide a secret. The sensor arrangement is configured to link the sensor signal to the secret to obtain a linked sensor signal, transmit the linked sensor signal to a communication partner using the communication device, obtain a test signal from the communication partner using the communication device, and perform a check to determine whether the test signal comprises the secret.

Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.

Abstract: A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.

Abstract: A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.

Abstract: UWB Antenna comprising: a first substrate layer (10); a second substrate layer (20); a conductive ground layer (300) arranged on a first side of the first substrate layer and connected to a ground terminal; a first conductive layer (100) arranged between the first substrate layer (10) and the second substrate layer (20), wherein a central portion (140) of the first conductive layer (100) is connected to the feed terminal (3), wherein the first conductive layer (100) has a shape with a plurality of arms extending radially from the central portion (140), wherein the plurality of arms (110, 120, 130) is connected in its distal portion (111, 121, 131) with the ground layer (300); a second conductive layer (200) arranged on a second side of the second substrate layer (20, 20?), wherein the layers (10, 20, 100, 200, 300) are realised with a multilayer circuit board.

Abstract: An ion shuttling system includes a plurality of first electrodes connected to a system configured to selectively provide an ion movement control voltage to each electrode of the plurality of first electrodes, a voltage source configured to provide one or more compensation voltages, a plurality of compensation electrodes comprising a plurality of compensation electrode pairs, where each compensation electrode pair of the plurality of compensation electrode pairs is associated with one or more different first electrodes of the plurality of first electrodes, and a plurality of switches, where each switch of the plurality of switches is connected at a respective first node to a compensation electrode of the plurality of compensation electrodes and is configured to selectively connect the respective compensation electrode to the voltage source.

Abstract: A multiphase inverter apparatus includes: an insulating substrate; at least one low voltage bus and at least one high voltage bus on a first surface of the insulating substrate; a plurality of half-bridge circuits, each half-bridge circuit being electrically coupled between a respective one of the at least one low voltage bus and a respective one of the at least one high voltage bus; and a phase output lead for each half-bridge circuit. For each half bridge circuit, the phase output lead is arranged on and electrically coupled to at least one packaged low side switch and at least one packaged high side switch of the half bridge circuit such that each packaged low side switch and each packaged high side switch is arranged vertically between the phase output lead and the first surface of the insulating substrate.

Abstract: An electronic chip is disclosed. In one example, the electronic chip comprises a substrate comprising a central portion and an edge portion around at least part of the central portion. An active region is arranged in the central portion. A crack guiding structure combined with a crack stop structure is provided, both being arranged in the edge portion.

Abstract: A magnetic field sensor includes a sensor and a processing circuit. The sensor is designed to generate on the basis of a varying magnetic field an oscillation signal that fluctuates around a mean value. The processing circuit is designed to generate an output signal on the basis of the oscillation signal. The processing circuit is designed, in a high-resolution mode different than a low-resolution mode, in each case to generate a mean value crossing pulse in the output signal when the oscillation signal attains the mean value, and to generate in each case a limit value crossing pulse in the output signal when the oscillation signal attains at least one limit value different than the mean value. A pulse width of at least either the mean value crossing pulse or the limit value crossing pulse is set to indicate that the magnetic field sensor is operating in the high-resolution mode.