Abstract: A semiconductor device includes a semiconductor die having a vertical transistor device with a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode, A second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Abstract: A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between first and second terminals, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. One first diode is electrically coupled in parallel to each switching device of the first type. One second diode is electrically coupled in parallel to each switching device of the second type. The switching devices are arranged in a power semiconductor module having first and second longitudinal sides and first and second narrow sides. The first type switching devices and first diodes are arranged alternatingly in one row along the first longitudinal side. The second type switching devices and second diodes are arranged alternatingly in another row along the second longitudinal side. An axis of symmetry that extends perpendicular to the first and second narrow sides.

Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

Abstract: A gas sensing device includes one or more chemo-resistive gas sensors; one or more heat sources, wherein the gas sensors are heated according to one or more first temperature profiles during the recovery phases and according to one or more second temperature profiles during the sense phases; a preprocessing processor for generating preprocessed signal samples; a feature extraction processor for extracting one or more feature values from the received preprocessed signal samples; and a gas concentration processor for creating a sensing result, wherein the gas concentration processor includes a classification processor for outputting a class decision value, wherein the classification processor is configured for outputting a confidence value, wherein the classification processor includes a first trained model based algorithm processor, wherein the gas concentration processor comprises a quantification processor for creating an estimation value, and wherein the quantification processor comprises a second trained m

Abstract: In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.

Abstract: According to one configuration, a fabricator receives magnetic permeable material and fabricates an apparatus to include a multi-dimensional arrangement of electrically conductive paths to extend through the magnetic permeable material. Each of the electrically conductive paths is a respective inductive path.

Abstract: A power semiconductor component for voltage limiting includes a rear-side base zone electrically contacted with a rear-side electrode and a front-side base zone electrically contacted with a front-side electrode. At least one switch-on structure is embedded at least into one of the rear-side base zone and the front-side base zone and is electrically contacted by the electrode contacting the embedding base zone. At least one triggering structure is provided as a breakdown structure of a first type, present between the front-side and rear-side electrodes. At least one further triggering structure is provided as a breakdown structure of a second type, present between the front-side and rear-side electrodes. The front-side and rear-side electrodes are each electrically conductively pressure-contacted by an electrically conductive contact plate at least one of which functions as a heat sink for dissipating heat generated in the semiconductor body.

Abstract: A magnetic field sensor includes a sensor and a processing circuit. The sensor is designed to generate on the basis of a varying magnetic field an oscillation signal that fluctuates around a mean value. The processing circuit is designed to generate an output signal on the basis of the oscillation signal. The processing circuit is designed, in a high-resolution mode different than a low-resolution mode, in each case to generate a mean value crossing pulse in the output signal when the oscillation signal attains the mean value, and to generate in each case a limit value crossing pulse in the output signal when the oscillation signal attains at least one limit value different than the mean value. A pulse width of at least either the mean value crossing pulse or the limit value crossing pulse is set to indicate that the magnetic field sensor is operating in the high-resolution mode.

Abstract: A magnetic sensor system includes a toothed wheel configured to rotate about a rotation axis that extends in an axial direction, wherein the toothed wheel includes a plurality of teeth and a plurality of notches arranged that define a circumferential perimeter, wherein the toothed wheel further includes an interior cavity arranged within the circumferential perimeter; a front-bias magnet arranged within the interior cavity of the toothed wheel, wherein the front-bias magnet is rotationally fixed and is magnetized with a magnetization direction that extends along a radial axis of the toothed wheel; and a magnetic sensor arranged exterior to the toothed wheel, wherein the magnetic sensor includes a sensor element arranged on the radial axis that coincides with the magnetization direction of the front-bias magnet and the first sensor element is sensitive to a magnetic field of the front-bias magnet that is aligned with the radial axis.

Abstract: In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

Abstract: Implementations relate to a sensor assembly for determining rotation about an axis and linear movement parallel to the axis. The sensor assembly comprises a magnetic structure comprising a north pole radially displaced from the axis and a south pole radially displaced from the axis and opposite to the north pole. The north pole and the south pole of the magnet extend radially into the direction of the axis at an axial end of the sensor assembly. The sensor assembly further comprises at least one sensor element sensitive to magnetic fields radially between the north pole and the south pole.

Abstract: In accordance with an embodiment, a method of operating a radar system includes receiving radar configuration data from a host, and receiving a start command from the host after receiving the radar configuration data. The radar configuration data includes chirp parameters and frame sequence settings. After receiving the start command, configuring a frequency generation circuit is configured with the chirp parameters and radar frames are triggered at a preselected rate.

Abstract: A method for fabricating packaged semiconductor devices is disclosed. In one example the method comprises providing a plurality of semiconductor dies, the semiconductor dies being arranged in an array on a carrier such that a first side of the semiconductor dies faces the carrier and such that an empty space is arranged laterally besides each semiconductor die. A substrate comprising a plurality of conductive elements is arranged over the plurality of semiconductor dies such that a conductive element is arranged in the respective empty space besides each one of the semiconductor dies. The plurality of semiconductor dies are molded over to form a molded body, and singulating packaged semiconductor devices from the molded body by cutting through the molded body.

Abstract: According to some embodiments, an apparatus comprises a multi-level power converter configured to convert an input voltage to an output voltage, wherein the multi-level power converter comprises one or more switching groups, wherein a switching group of the one or more switching groups comprises a pair of switches and a flying capacitor, and a controller configured to determine a duty reference for the switching group, determine a duty correction factor for the switching group based upon a flying capacitor voltage error of the flying capacitor, determine a sign correction signal based on a flying capacitor ripple voltage, and determine a duty command for activating the pair of switches based on the duty reference, the duty correction factor, and the sign correction signal.

Abstract: A method to secure boot an electronic device is disclosed according to some embodiments. The method includes receiving a request to initiate a boot sequence using memory content stored in a non-volatile memory circuit. A secure boot circuit receives verification data from the non-volatile memory circuit indicating the memory content. The verification data includes an error correction code for the memory content without including all of the memory content. A cryptographic hashing operation is performed to the error correction code in the secure boot circuit to obtain a digest of the error correction code. The digest is compared with a pre-stored reference digest to generate a verification signal. The verification signal is provided to the electronic device indicating whether the boot sequence passes the verification.

Abstract: A switch device including a semiconductor substrate is provided. A trench is formed in the substrate, and a phase change material is provided at least partially in the trench. A heater for heating the phase change material is also provided.

Abstract: An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.

Abstract: An imaging system includes an illumination element for emitting light and an imaging sensor having at least one photo-sensitive element that includes a first element with a modifiable first charge level and a second element with a modifiable second charge level. Control circuitry is configured to, during a first phase, control the illumination element to emit light towards a scene and drive the photo-sensitive element such that charge carriers generated in the photo-sensitive element by light received from the scene modify the first charge level. The control circuitry is configured to, during a second phase, control the illumination element to pause emission of the light and drive the photo-sensitive element such that charge carriers generated in the photo-sensitive element by light received modify the second charge level, and to generate a gray-scale image of the scene based on the first and second charge levels.

Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.