Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

Abstract: A semiconductor device includes a die carrier, a semiconductor die disposed on a main face of the die carrier, the semiconductor die including one or more contact pads, an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier, an insulation layer covering the encapsulant, and one or more electrical interconnects, each being connected with one of the one or more contact pads of the semiconductor die and extending through the encapsulant.

Abstract: A method of producing a semiconductor component includes: providing a silicon-based substrate; depositing an oxide layer on the silicon-based substrate; depositing a polycrystalline silicon layer on the oxide layer and simultaneously a crystalline silicon layer on the silicon-based substrate; producing an electronic component based on the polycrystalline silicon layer; and mounting a glass- or silicon-based lid on the crystalline silicon layer.

Abstract: A semiconductor device includes a semiconductor body, a vertical transistor arranged in a first device region of the semiconductor body, and a lateral transistor arranged in a second device region of the semiconductor body. The vertical transistor includes a plurality of drift regions of a first doping type and a plurality of compensation regions of a second doping type complementary to the first doping type. The drift regions and the compensation regions are arranged alternately in a lateral direction of the semiconductor body. The second device region includes a well-like structure of the second doping type surrounding a first semiconductor region of the first doping type. The lateral transistor includes device regions arranged in the first semiconductor region.

Abstract: The present disclosure describes a device for determining information regarding a connection of a circuit component that is connected to an output of a regulator in order to reduce fluctuations of an output signal at the output of the regulator. The device includes a processing unit that is configured to generate a statistical value that is a measure of fluctuations of the measurement signals, and thus of the output signal at the output of the regulator, based on a plurality of measurement signals, each of which has information regarding the output signal of the regulator and is recorded while a load component generates an electrical load at the output of the regulator. The processing unit is configured to compare the statistical value with a limit value and to determine the information regarding the connection of the circuit component based on the result of the comparison.

Abstract: Systems, methods, circuits, and devices for data protection are provided. In one example, a data processing device incudes a Physical Unclonable Function (PUF) source that is configured to generate PUF values, a bus, a plurality of bus access components that are configured to access the bus, and a masking information generation circuit. The masking information generation circuit is configured to generate masking information for at least one pair of bus access components using at least one PUF value and to transmit said information to the bus access components. The pair is configured in such a way that one bus access component masks the data according to the masking information generated for the pair before the data is sent over the bus and the other bus access component de-masks the data received over the bus according to the masking information generated for the pair.

Abstract: A transistor device includes a semiconductor body having a substantially planar main surface, a source region extending to the main surface and having a first conductivity type, a body region extending to the main surface and having a second conductivity type, a drain region extending to the main surface and having the first conductivity type, a drift region having the first conductivity type, and a gate electrode arranged on the main surface laterally between the source and drain regions and electrically insulated from the semiconductor body by an insulation structure. The insulation structure includes a gate dielectric arranged on the main surface and a shallow trench arranged in the drift region and filled with electrically insulating material. The shallow trench has at least partly a wedge shape and the electrically insulating material has an upper surface that is substantially planar and extends substantially parallel to the main surface.

Abstract: An inductive sensor may include a first angle measurement path associated with determining an angular position based on a first set of input signals. The inductive sensor may include a second angle measurement path associated with determining an angular position based on a second set of input signals. The inductive sensor may include an amplitude regulation path associated with regulating amplitudes of a set of output signals. The inductive sensor may include a safety path associated with performing one or more safety checks. Each safety check of the one or more safety checks may be associated with at least one of the first angle measurement path, the second angle measurement path, or the amplitude regulation path.

Abstract: A radar device is provided comprising a first processing unit, a radar circuitry, at least one security circuitry, at least one secure memory, and a secure interface arranged for communicating with a second processing unit that is external to the radar device, wherein the first processing unit is arranged to configure and/or run the radar device based on parameters obtained via the secure interface from the second processing unit.

Abstract: A power semiconductor system includes: a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board; and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor includes windings patterned into a second printed circuit board of the inductor module.

Abstract: A voltage regulating circuit including a conversion circuit configured to convert a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a predefined operating limiting voltage, and a regulator configured to receive the filtered analog voltage as regulation variable and to regulate an output voltage of the voltage regulating circuit to a predefined desired voltage.

Abstract: An RF switch device includes transistors coupled in series forming an RF conductive current path; a first resistive bias network forming a DC conductive bias path between gate nodes of the plurality of transistors; and a first ESD bias component coupled between the RF conductive current path and the first resistive bias network, wherein the first ESD bias component provides a DC conductive path between the RF conductive current path of the RF switch device and the first resistive bias network during an ESD event.

Abstract: An apparatus includes a controller. The controller monitors a magnitude of voltage powering a first dynamic load disposed in a series circuit path of multiple dynamic loads. The controller compares the magnitude of the voltage to a reference voltage. Based on the comparing, the controller controls operation of multiple power converter phases in a power converter to maintain a magnitude of the voltage powering the first dynamic load.

Abstract: A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.

Abstract: A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.

Abstract: Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.

Abstract: A time-of-flight (ToF) image sensor system includes a pixel array, where each pixel of the pixel array is configured to receive a reflected modulated light signal and to demodulate the reflected modulated light signal to generate an electrical signal; a plurality of analog-to-digital converters (ADCs), where each ADC is coupled to at least one assigned pixel of the pixel array and is configured to convert a corresponding electrical signal generated by the at least one assigned pixel into an actual pixel value; and a binning circuit coupled to the plurality of ADCs and configured to generate at least one interpolated pixel, where the binning circuit is configured to generate each of the at least one interpolated pixel based on actual pixel values corresponding to a different pair of adjacent pixels of the pixel array, each of the at least one interpolated pixel having a virtual pixel value.

Abstract: An electronic inhalation apparatus including a body having a chip module accommodating region which is at least partially surrounded by a folding structure. When a chip module is accommodated in the chip module accommodating region, the folding structure is bent around the chip module in order to fasten the chip module.

Abstract: In some implementations, a sensor may determine a delay latency value associated with an amount of time from completion of a set of sensor tasks to an actual time of reception of a trigger to selectively transmit or sample sensor data. The sensor may calculate a deviation of the delay latency value from a target delay latency. The sensor may transmit a data frame including an indication associated with the deviation of the delay latency value from the target delay latency.

Abstract: A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n-1, and the third number is 1, the total number of resistors is 2n.