Abstract: A sensor system may include a first magnet arranged such that a position of the first magnet corresponds to a position of a trigger element on a linear trajectory. The sensor system may include a second magnet arranged such that a position of the second magnet corresponds to a selected position of a selection element. The sensor system may include a magnetic sensor to detect a strength of a first magnetic field component, a strength of a second magnetic field component, and a strength of a third magnetic field component. The magnetic sensor may be further to determine the position of the trigger element based on the strength of the first magnetic field component and the strength of the second magnetic field component, and to determine the selected position of the selection element based on the strength of the third magnetic field component.

Abstract: In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.

Abstract: A semiconductor device includes a semiconductor die having a vertical transistor device with a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode, A second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Abstract: A power module includes a metal frame having a first and second device attach pads, first and second semiconductor packages each having an encapsulant body, a die pad exposed at a lower surface of the encapsulant body, a plurality of leads protruding out from the encapsulant body, and a potting compound that encapsulates both of the first and second semiconductor packages and partially covers the metal frame. The first semiconductor package is mounted on the metal frame such that the die pad of the first semiconductor package faces and electrically contacts the first device attach pad. The second semiconductor package is mounted on the metal frame such that the die pad of the second semiconductor package faces and electrically contacts the second device attach pad. The plurality of leads from each of the first and second semiconductor packages are electrically accessible from outside of the potting compound.

Abstract: A power semiconductor component for voltage limiting includes a rear-side base zone electrically contacted with a rear-side electrode and a front-side base zone electrically contacted with a front-side electrode. At least one switch-on structure is embedded at least into one of the rear-side base zone and the front-side base zone and is electrically contacted by the electrode contacting the embedding base zone. At least one triggering structure is provided as a breakdown structure of a first type, present between the front-side and rear-side electrodes. At least one further triggering structure is provided as a breakdown structure of a second type, present between the front-side and rear-side electrodes. The front-side and rear-side electrodes are each electrically conductively pressure-contacted by an electrically conductive contact plate at least one of which functions as a heat sink for dissipating heat generated in the semiconductor body.

Abstract: In accordance with an embodiment, a method of operating a radar system includes receiving radar configuration data from a host, and receiving a start command from the host after receiving the radar configuration data. The radar configuration data includes chirp parameters and frame sequence settings. After receiving the start command, configuring a frequency generation circuit is configured with the chirp parameters and radar frames are triggered at a preselected rate.

Abstract: In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

Abstract: A method for fabricating packaged semiconductor devices is disclosed. In one example the method comprises providing a plurality of semiconductor dies, the semiconductor dies being arranged in an array on a carrier such that a first side of the semiconductor dies faces the carrier and such that an empty space is arranged laterally besides each semiconductor die. A substrate comprising a plurality of conductive elements is arranged over the plurality of semiconductor dies such that a conductive element is arranged in the respective empty space besides each one of the semiconductor dies. The plurality of semiconductor dies are molded over to form a molded body, and singulating packaged semiconductor devices from the molded body by cutting through the molded body.

Abstract: A magnetic sensor system includes a toothed wheel configured to rotate about a rotation axis that extends in an axial direction, wherein the toothed wheel includes a plurality of teeth and a plurality of notches arranged that define a circumferential perimeter, wherein the toothed wheel further includes an interior cavity arranged within the circumferential perimeter; a front-bias magnet arranged within the interior cavity of the toothed wheel, wherein the front-bias magnet is rotationally fixed and is magnetized with a magnetization direction that extends along a radial axis of the toothed wheel; and a magnetic sensor arranged exterior to the toothed wheel, wherein the magnetic sensor includes a sensor element arranged on the radial axis that coincides with the magnetization direction of the front-bias magnet and the first sensor element is sensitive to a magnetic field of the front-bias magnet that is aligned with the radial axis.

Abstract: Implementations relate to a sensor assembly for determining rotation about an axis and linear movement parallel to the axis. The sensor assembly comprises a magnetic structure comprising a north pole radially displaced from the axis and a south pole radially displaced from the axis and opposite to the north pole. The north pole and the south pole of the magnet extend radially into the direction of the axis at an axial end of the sensor assembly. The sensor assembly further comprises at least one sensor element sensitive to magnetic fields radially between the north pole and the south pole.

Abstract: An imaging system includes an illumination element for emitting light and an imaging sensor having at least one photo-sensitive element that includes a first element with a modifiable first charge level and a second element with a modifiable second charge level. Control circuitry is configured to, during a first phase, control the illumination element to emit light towards a scene and drive the photo-sensitive element such that charge carriers generated in the photo-sensitive element by light received from the scene modify the first charge level. The control circuitry is configured to, during a second phase, control the illumination element to pause emission of the light and drive the photo-sensitive element such that charge carriers generated in the photo-sensitive element by light received modify the second charge level, and to generate a gray-scale image of the scene based on the first and second charge levels.

Abstract: A switch device including a semiconductor substrate is provided. A trench is formed in the substrate, and a phase change material is provided at least partially in the trench. A heater for heating the phase change material is also provided.

Abstract: According to some embodiments, an apparatus comprises a multi-level power converter configured to convert an input voltage to an output voltage, wherein the multi-level power converter comprises one or more switching groups, wherein a switching group of the one or more switching groups comprises a pair of switches and a flying capacitor, and a controller configured to determine a duty reference for the switching group, determine a duty correction factor for the switching group based upon a flying capacitor voltage error of the flying capacitor, determine a sign correction signal based on a flying capacitor ripple voltage, and determine a duty command for activating the pair of switches based on the duty reference, the duty correction factor, and the sign correction signal.

Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

Abstract: A method to secure boot an electronic device is disclosed according to some embodiments. The method includes receiving a request to initiate a boot sequence using memory content stored in a non-volatile memory circuit. A secure boot circuit receives verification data from the non-volatile memory circuit indicating the memory content. The verification data includes an error correction code for the memory content without including all of the memory content. A cryptographic hashing operation is performed to the error correction code in the secure boot circuit to obtain a digest of the error correction code. The digest is compared with a pre-stored reference digest to generate a verification signal. The verification signal is provided to the electronic device indicating whether the boot sequence passes the verification.

Abstract: A combined MicroElectroMechanical structure (MEMS) includes a first piezoelectric membrane having one or more first electrodes, the first piezoelectric membrane being affixed between a first holder and a second holder; and a second piezoelectric membrane having an inertial mass and one or more second electrodes, the second piezoelectric membrane being affixed between the second holder and a third holder.

Abstract: An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.

Abstract: In an embodiment, a method includes: generating a displacement signal indicative of a distension of a surface of a skin; determining a temperature of the skin using a temperature sensor; during a calibration time interval, collecting a plurality of distension values from the displacement signal, the plurality of distension values associated with a respective plurality of temperature values determined using the temperature sensor, the plurality of temperature values being indicative of a temperature change of the skin; determining compensation coefficients associated with the plurality of temperature values; and after the calibration time interval, collecting a first distension value from the displacement signal, determining a first temperature value using the temperature sensor, and determining a blood pressure based on the first distension value, the first temperature value, and the determined compensation coefficients.

Abstract: A method for determining a calibrated measurement value for a concentration of the target gas comprises obtaining a measurement signal based on the concentration of the target gas. The method further comprises determining the calibrated measurement value based on the measurement signal and based on a calibration model. The calibration model is based on calibration data of a plurality of test sensor units having the same type as the sensor unit.

Abstract: This disclosure is directed to a dual gate metal oxide semiconductor field effect transistor (MOSFET) device formed in a semiconductor material, as well as circuits and techniques for using the dual gate MOSFET device. In some examples, the dual gate MOSFET device may comprise a first MOSFET formed in the semiconductor material, and a second MOSFET formed in the semiconductor material, wherein the first MOSFET and the second MOSFET are arranged in parallel in the semiconductor material, wherein the first MOSFET and the second MOSFET include a common drain node and a common source node, and wherein the first MOSFET and the second MOSFET define different transfer characteristics.