Abstract: A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.

Abstract: In an embodiment, a method for testing a millimeter-wave radar module includes: providing power to the millimeter-wave radar module; performing a plurality of tests indicative of a performance level of the millimeter-wave radar module; comparing respective results from the plurality of tests with corresponding test limits; and generating a flag when a result from a test of the plurality of test is outside the corresponding test limits, where performing the plurality of tests includes: transmitting a signal with a transmitting antenna coupled to a millimeter-wave radar sensor, modulating the transmitted signal with a test signal, and capturing first data from a first receiving antenna using an analog-to-digital converter of the millimeter-wave radar sensor, where generating the flag includes generating the flag based on the captured first data.

Abstract: A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area AQ, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 m?*cm2/AQ.

Abstract: A semiconductor package includes: a semiconductor die attached to a lead frame and having a first bond pad at a side of the semiconductor die facing away from the lead frame; a metal clip having a first bonding region attached to the first bond pad by a solder joint, the metal clip providing an electrical pathway to the first bond pad; and an additional electrical pathway to the first bond pad. A first end of the additional electrical pathway is attached to the first bond pad. At one or more locations between the first end and a second end of the additional electrical pathway, the additional electrical pathway is attached to a surface of the first bonding region of the metal clip that faces away from the first bond pad. Methods of producing the semiconductor package are also described.

Abstract: It is suggested to process radar signals including: (i) receiving reception signals via at least one antenna of a first receiving circuit; (ii) determining an interim result by processing the reception signals via a frequency transformation; (iii) determining an error compensation vector based on the interim result and an expected characteristic; and (iv) applying the error compensation vector on other reception signals that have been processed via the frequency transformation.

Abstract: A semiconductor package includes an encapsulant body; a first electrically conductive element having an outwardly exposed metal surface; a first carrier substrate having a first electrically conductive layer, a second electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the first electrically conductive element and the first electrically conductive layer; a power semiconductor chip between the first electrically conductive element and the first electrically conductive layer; and a second electrically conductive spacer between the first electrically conductive element and the power semiconductor chip, a first carrier region of the first electrically conductive layer is connected to a first power terminal, a second carrier region of the first electrically conductive layer is alongside the first carrier region and is connected to a second power terminal, a first region of the first electrically conductive element is

Abstract: A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.

Abstract: In accordance with an embodiment, a method of operating a radar system includes receiving radar configuration data from a host, and receiving a start command from the host after receiving the radar configuration data. The radar configuration data includes chirp parameters and frame sequence settings. After receiving the start command, configuring a frequency generation circuit is configured with the chirp parameters and radar frames are triggered at a preselected rate.

Abstract: A method and slave devices are disclosed in which an address assignment to slave devices takes place with the aid of a collision detection. The slave device receives an initialization signal, transmits an identifier over a bus in response to the initialization signal, checks whether a collision occurs on the bus when transmitting the identifier, and if a collision occurs, places the slave device into an inactive state, and if no collision occurs, receives an address for the slave device after the transmission of the identifier.

Abstract: A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region.

Abstract: A cryostat socket for holding an ion trap device mounted on a substrate in a cryostat includes a housing frame provided for pre-assembly in the cryostat. A pin insert is arranged in the housing frame. The pin insert includes a base plate and contact pins. The contact pins are arranged in an array. A housing cover has a receptacle for the substrate. The housing cover, when assembled with the housing frame, exerts a compressive force on a front side of the substrate by which a rear side of the substrate is pressed onto the contact pins.

Abstract: A solder material is provided. In one or more examples, the solder material may include metal solder particles, a carboxylic acid, and an alcohol selected from the group consisting of methanol, ethanol, propan-1-ol, propan-2-ol, 2-methyl-1-propanol, butan-1-ol, pentan-1-ol, 1,2-propanediol, 1,3-propanediol, and glycerol.

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes a leadframe for flip chip attaching a semiconductor die thereon that comprises a rectangular area segmented into individual pads. The individual pads comprise a first pad, a second pad, and a third pad, wherein the first pad is larger than the second pad and larger than the third pad. The second pad is located in a first corner area of the rectangular area and the third pad is located in a second corner area of the rectangular area. The second corner area is located diagonally opposite to the first corner area.

Abstract: An electronic device is disclosed. In one example, the electronic device comprises a laminate carrier comprising a plurality of laminated layers, an electronic component embedded in the laminate carrier, and an at least partially electrically conductive pin extending partially inside the laminate carrier and partially protruding beyond the laminate carrier. The pin is electrically coupled with the electronic component.

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes an encapsulation material at least partially encapsulating a semiconductor component of the semiconductor device. The semiconductor device further includes a first lead protruding out of a first side surface of the encapsulation material and a second lead protruding out of a second side surface of the encapsulation material opposite to the first side surface. The first lead includes a first notch aligned with the first side surface of the encapsulation material. The first notch faces away from a further lead protruding out of the first side surface of the encapsulation material.

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

Abstract: A method for operating a power converter and a control circuit are disclosed. The method includes, in a power converter including an input, a converter stage, a first switch connected between the input and the converter stage, a second switch connected between input nodes of the converter stage, and an output capacitor connected between output nodes of the converter stage: detecting an operating state of the power converter; and operating the power converter in a first operating mode when the power converter is in a first operating state. Operating the power converter in the first operating mode includes regulating an input current received at the input by a switched-mode operation of the first and second electronic switches.

Abstract: A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.

Abstract: A dual active bridge circuit includes a primary side circuit including first high-side transistor and a first low-side transistor electrically coupled at a first node, and an energy transfer inductor coupled to the first node and configured to provide an inductor current based on a voltage differential across the energy transfer inductor. A secondary side circuit includes a second high-side transistor and a second low-side transistor electrically coupled at a second node. A transformer is configured to transfer energy from the primary side circuit to the secondary side circuit based on the inductor current. A controller is configured to drive each of the transistors between respective switching states with a same duty cycle to control the voltage differential across the energy transfer inductor. The same duty cycle is less than 50% such that all of the transistors are simultaneously off for a predetermined interval.

Abstract: An isolated power converter includes: a transformer having primary winding and first and second auxiliary windings on the primary side; a converter stage configured to convert a DC input for driving the primary winding and having a resonant capacitor electrically connected to the primary winding; a controller configured to control switching of the converter stage; and a voltage supply circuit configured to select a first voltage as a supply voltage for the controller if a voltage proportional to a secondary side voltage of the transformer is at a first level or select a second voltage as the supply voltage if the voltage proportional to the secondary side voltage is at a second level greater than the first level. The first voltage corresponds to a summation of voltages across the first auxiliary winding and the resonant capacitor. The second voltage corresponds to a voltage across the second auxiliary winding.