Abstract: A method of manufacturing an electronic module assembly includes forming the electronic module assembly, wherein the electronic module assembly comprises a plurality of internal exposed surfaces, a plurality of external exposed surfaces, at least one internal cavity, and an internal heat source configured to generate heat internally within the electronic module assembly; dipping the electronic module assembly into a thermally conductive material to coat the plurality of internal exposed surfaces and the plurality of external exposed surfaces and to at least partially fill the at least one internal cavity; and curing the thermally conductive material formed on the plurality of internal exposed surfaces and the plurality of external exposed surfaces and filled within the at least one internal cavity to form a thermally conductive layer, wherein the thermally conductive layer is formed as a one-piece integral member.

Abstract: A package including a component for a package is disclosed. In one example, wherein the component comprises a functional body, and a wettability layer arranged on a main surface of the functional body and configured for promoting wetting of a connection medium to be applied on the wettability layer for connecting the component with a further component of the package. The wettability layer has a lateral circumference at least part of which having a concave edge.

Abstract: A semiconductor device includes an IGBT in an IGBT portion of a semiconductor body and a diode in a diode portion of the semiconductor body. The diode includes an anode region of a first conductivity type and confined by diode trenches along a first lateral direction. Each of the diode trenches includes a diode trench electrode and a diode trench dielectric. A first contact groove extends into the anode region along a vertical direction from the first surface of the semiconductor body. An anode contact region of the first conductivity type adjoins a bottom side of the first contact groove. A cathode contact region of a second conductivity type adjoins a second surface of the semiconductor body opposite to the first surface. The IGBT includes a gate trench including a gate electrode and a gate dielectric, a source region, an emitter electrode, a drift region, and a second contact groove.

Abstract: A system and method for the acoustic detection of cracks in a semiconductor substrate is disclosed. In one example, the system includes a force generating unit configured to apply a force onto the semiconductor substrate, a detector unit comprising a resonating indenter and an acoustic emission sensor coupled to the resonating indenter, and an evaluation unit configured to evaluate acoustic signals detected by the detector unit and configured to determine whether a crack has occurred based on the detected signals. The resonating indenter is configured to contact the semiconductor substrate at a lateral distance from the force generating unit, and wherein the force generating unit and the resonating indenter are configured to contact the semiconductor substrate on the same side.

Abstract: The present disclosure relates to circuits for detecting a line short circuit and/or a line interruption in a differentially operated line network, comprising at least one control circuit configured to control at least one common-mode signal of the differentially operated line network vis-à-vis a predefined common-mode signal variable and to indicate a line short circuit and/or a line interruption in the differentially operated line network if at least one control or controlled variable of the control circuit exceeds a predefined threshold value.

Abstract: A method of forming a silicon layer includes introducing a source gas containing a precursor material and a carrier gas into a reactor, controlling a gas flow of the source gas through a first main flow controller unit in response to a change of a concentration of the precursor material in the source gas, introducing an auxiliary gas into the reactor, and controlling a gas flow of the auxiliary gas through a second main flow controller unit such that a total gas flow of the source gas and the auxiliary gas into the reactor is held constant when the gas flow of the source gas changes.

Abstract: A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.

Abstract: The disclosure provides a microcontroller which has an internal timing device for generating an internal clock signal, at least one terminal contact for receiving an external clock signal, a clock changing device and a timer module, which is electrically conductively connected to the at least one terminal contact and to the internal timing device and, after the microcontroller has been switched on, is set up to determine a frequency of the external clock signal by means of the clock signal, and to determine at least one parameter by means of which the clock changing device can be set up to change the external clock signal into a useful clock signal with a predefined frequency.

Abstract: A method for current measurement in a switching converter is described herein. In accordance with one embodiment, the method includes switching a first transistor on and off in accordance with a logic signal, wherein a load current passes through the first transistor while it is switched on. The method further includes providing—by a second transistor—a sense current that is indicative of the load current, wherein the second transistor is coupled to the first transistor so that the first and the second transistors are switched on and off simultaneously. Further, the method includes determining an end of a switch-on phase of the second transistor, and providing a current sense signal that represents the sense current between a first time instant, which corresponds to the determined end of the switch-on phase, and a second time instant, at which the logic signal signals a switch-off of the first transistor.

Abstract: A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

Abstract: An adaptive MEMS device includes a MEMS microphone and integrated circuitry, wherein the integrated circuitry is electrically connected to the MEMS microphone. The integrated circuitry reads out an output signal from the MEMS microphone and provides the output signal or a rendered output signal, via a first integrated interface, to an external processing device. Additionally, the integrated circuitry determines, at run-time, diagnostic data on the current condition of the MEMS device and provides, at run-time, the diagnostic data, via a second integrated interface, to the external processing device.

Abstract: In an embodiment, a method includes: transmitting a plurality of radar signals using a millimeter-wave radar sensor towards a target; receiving a plurality of reflected radar signals that correspond to the plurality of transmitted radar signals using the millimeter-wave radar; mixing a replica of the plurality of transmitted radar signals with the plurality of received reflected radar signals to generate an intermediate frequency signal; generating raw digital data based on the intermediate frequency signal using an analog-to-digital converter; processing the raw digital data using a constrained L dimensional convolutional layer of a neural network to generate intermediate digital data, where L is a positive integer greater than or equal to 2, and where the neural network includes a plurality of additional layers; and processing the intermediate digital data using the plurality of additional layers to generate information about the target.

Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

Abstract: A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

Abstract: A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

Abstract: An overvoltage protection device includes a semiconductor body including a substrate region disposed beneath an upper surface of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector includes a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.

Abstract: A sensor circuit, having a startup phase and an operation phase, includes: a sensor configured to generate a sensor signal based on a measured property, wherein the sensor signal has a frequency spectrum defined by a first frequency and a second frequency that is greater than the first frequency; a signal processing circuit including an analog-to-digital converter (ADC) configured to convert the sensor signal into a digital sensor signal; and an offset diagnosis circuit. The offset diagnosis circuit includes: a low pass filter having a cutoff frequency less than the first frequency and configured to generate a filtered signal based on the digital sensor signal; an offset register configured to store a startup signal value of the filtered signal during the startup phase; and an offset comparator circuit configured to set a threshold range based on the startup signal value for use during the operation phase.

Abstract: A power supply includes a controller. The controller controls switching of a first switch and a second switch in a power supply to regulate conveyance of energy from a primary winding of a transformer to a secondary winding of the transformer to generate an output voltage. To control generation of the output voltage, the controller receives a first signal generated at a first node coupling the first switch and the second switch. As discussed herein, the controller controls activation of the first switch to an ON state depending on a magnitude of the first signal. This disclosure provides improved reliability of power supply components (such as one or more switches) because such components are no longer stressed (or overstressed) due to body diode cross conduction.

Abstract: A power electronics system includes: a power semiconductor module with opposite first and second sides and lateral sides connecting the first and second sides. The power semiconductor module includes: at least one power semiconductor die forming at least one part of a half bridge circuit, an encapsulation encapsulating the power semiconductor die, and an external contact configured as a direct current contact of the half bridge circuit and exposed from the encapsulation at a lateral side of the power semiconductor module. A driver module arranged over the first side of the power semiconductor module is configured to control the half bridge circuit. A differential Hall sensor arranged over the external contact is configured to detect a direct current flowing through the external contact. The driver module is configured to modify a control pattern of the half bridge circuit based on a direct current value detected by the differential Hall sensor.

Abstract: An integrated circuit with galvanic isolation is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element configured to separate a first isolation domain from a second isolation domain and a first channel configured to transmit—in a first mode of operation and across the first isolation element—a logic signal from a first input in the first isolation domain to a first output in the second isolation domain. The first channel is further configured to transmit—in a second mode of operation and across the first isolation element—a serial data stream from the first input to a logic circuit in the second isolation domain, wherein the logic circuit is configured to receive—in the second mode of operation—the serial data stream and to store configuration information included in the serial data stream in a memory.