Abstract: A device for forming a housing for a power semiconductor module arrangement includes a mold. The mold includes a first cavity including a plurality of first openings and a second opening, the second opening being coupled to a runner system, wherein the runner system is configured to inject a mold material into the first cavity through the second opening. The device further includes a plurality of sleeves or hollow bushings, wherein a first end of each of the plurality of sleeves or hollow bushings is arranged in one of the first openings, and wherein a second end of each of the plurality of sleeves or hollow bushings extends to the outside of the mold, a heating element configured to heat the mold, and a cooling element configured to cool the plurality of sleeves or hollow bushings.

Abstract: An encapsulant for an electronic package is disclosed. In one example, the encapsulant comprises an electrically insulating matrix material, and a porous colorant in the matrix material.

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Abstract: A circuit includes one or more datastores configured to store a result register and a readout counter value and logic circuitry coupled to the one or more datastores. The logic circuitry is configured to cause, for a cycle of a plurality of cycles of a periodic signal, one or more analog-to-digital converters (ADCs) to store data to the result register and modify the readout counter value in response to the one or more ADCs storing the data to the result register for the cycle. In response to a read request for the data at the result register for the cycle, the logic circuitry is configured to output the data stored by the result register, output the readout counter value for the cycle, and, after the output of the readout counter value, set the readout counter value to a predetermined value.

Abstract: In some examples, a method of operating a circuit is described. The method may include performing a circuit function and estimating a probability of failure of the circuit based on one or more stress origination metrics, one or more stress victim events, and one or more initial state conditions.

Abstract: A method of forming a semiconductor package includes producing a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, providing a first load terminal on a first surface of the first semiconductor die and a second load terminal on a second surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die; providing a liner of dielectric material on the first semiconductor die; embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.

Abstract: A semiconductor device includes: a drift region of a first conductivity type in a semiconductor body having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; and trenches extending into the semiconductor body from the first main surface and patterning the semiconductor body into mesas. The trenches include: a first trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; a second trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; and a third trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes. Additional semiconductor device embodiments are described herein.

Abstract: In an embodiment, a method includes: receiving raw data from a millimeter-wave radar sensor; generating a first radar-Doppler image based on the raw data; generating a first radar point cloud based on the first radar-Doppler image; using a graph encoder to generate a first graph representation vector indicative of one or more relationships between two or more parts of the target based on the first radar point cloud; generating a first cadence velocity diagram indicative of a periodicity of movement of one or more parts of the target based on the first radar-Doppler image; and classifying an activity of a target based on the first graph representation vector and the first cadence velocity diagram.

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.

Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface and at least one transistor device structure, a source pad and a gate pad arranged on the first major surface, a drain pad and at least one further contact pad coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.

Abstract: Error correction is proposed in which a syndrome calculation is carried out in a code domain of a second code and an efficient error correction algorithm is carried out in a code domain of a first code.

Abstract: An apparatus comprises a power module housing. The power module housing includes a conductive substrate and a circuit board positioned overlying the conductive substrate. A gate driver is mounted to the circuit board. A power device is mounted to the conductive substrate and is controlled by the gate driver. The power module housing includes an insulation material electrically insulating the conductive substrate from the circuit board. A monitoring component is mounted to at least the conductive substrate and is operatively coupled to the gate driver and the power device.

Abstract: A radar semiconductor chip includes a radar circuit component configured to generate at least part of a frequency-modulated ramp signal or process at least part of a reflected frequency-modulated ramp signal according to a control parameter; a memory configured to store a sequencing program associated with regulating the control parameter, wherein the sequencing program specifies a first data source, external to the sequencing program, that is configured to provide a first data value corresponding to the control parameter; and a decoder configured to read the sequencing program, access the first data value from the first data source specified by the sequencing program, derive a first control value for the control parameter from the first data value, and provide the first control value to the radar circuit component. The radar circuit component regulates a controlled circuit function in accordance with the control parameter based on the first control value.

Abstract: pa The method of processing a semiconductor wafer includes forming one or more epitaxial layers over its first main surface. It also involves forming one or more porous layers within the semiconductor wafer or within the epitaxial layers. Together, the semiconductor wafer, the epitaxial layer(s), and the porous layer(s) form a substrate. Next, doped regions of a semiconductor device are formed within the epitaxial layer(s). After forming these doped regions, a non-porous part of the semiconductor wafer is separated from the rest of the substrate along the porous layer(s).

Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: A method of forming a semiconductor package includes providing a first metal substrate; and mounting a stacked arrangement on the first metal substrate, the stacked arrangement comprising a semiconductor die, wherein mounting the stacked arrangement includes: providing a first layer of attachment material between the first metal substrate and the stacked arrangement; and providing a second layer of attachment material within the stacked arrangement at an interface with the semiconductor die, wherein at least one of the first and second layers of attachment material is a compressible layer that includes one or more elastomeric elements embedded within a matrix of solder material.

Abstract: A power semiconductor device includes, an active area that conducts load current between first and second load terminal structures, a drift region, and a backside region that includes, inside the active area, first and second backside emitter zones one or both of which includes: first sectors having at least one first region of a second conductivity type contacting the second load terminal structure and a smallest lateral extension of at most 50 ?m; and/or second sectors having a second region of the second conductivity type contacting the second load terminal structure and a smallest lateral extension of at least 50 ?m. The emitter zones differ by at least of: the presence of first and/or second sectors; smallest lateral extension of first and/or second sectors; lateral distance between neighboring first and/or second sectors; smallest lateral extension of the first regions; lateral distance between neighboring first regions within the same first sector.

Abstract: A module includes: an electrically insulative housing; a driver circuit enclosed in the housing and configured to drive a control terminal of a power switch; a wireless communication circuit enclosed in the housing and configured to receive, through the housing, wireless control information transmitted to the module; and a wireless energy receiver enclosed in the housing and configured to receive, through the housing, energy wirelessly transmitted to the module, and to supply power to the driver circuit. The driver circuit is configured to drive the control terminal of the power switch based on the wireless control information received by the wireless communication circuit. A power electronic assembly that incorporates one or more of the modules and a corresponding power conversion control circuit are also described.

Abstract: An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.