Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.

Abstract: The present invention includes a Mach-Zehnder modulator (MZM) linear driver configured in a differential form with two waveguides carrying two traveling waves which supports a two-channel spectral combiner integrated with a wavelength locker. By coupling a DC current source supplied with a modulation voltage with each segment thereof for providing electrical modulation signal overlapping with each of the two traveling waves. The modulated traveling waves in the two waveguides then are combined in one output signal by a multimode interference coupler. Two optical signals at ITU grid channels are separately modulated by two MZMs and combined into a silicon waveguide-based delayed-line interferometer built on a SOI substrate to produce an output signal having a free spectral range equal to twice of the spacing of the two ITU grid channels. Two dither signals can be added respectively to the two optical signals for identifying and locking corresponding two channel wavelengths.

Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

Abstract: A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.

Abstract: A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.

Abstract: A compact polarization beam rotator includes a converter waveguide comprising a first segment and a second segment both in corresponding taper rib shapes sharing a first middle plane and configured to receive an input optical signal with TM polarization mode from an input plane and convert the TM polarization mode to TE1 polarization mode comprising a first arm mode and a second arm mode at a second middle plane. The polarization beam rotator additionally includes a splitter waveguide coupled to the second middle plane for separating the first arm mode and the second arm mode at a third plane respectively coupled to a first branch waveguide to deliver the first arm mode in phase and a second branch waveguide to reverse the second arm mode phase by 180°, and a 2×1 MMI coupler waveguide to combine both arm modes in phase to an output optical signal with TE polarization mode.

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Abstract: An apparatus for handling a fiber-array to be attached with a silicon-photonics chip. The apparatus includes a bottom-plate having a first trench formed with two first branches connected to two first recessed regions at a first end and one second branch straight to a second end thereof and a second trench sharing the same second branch and having two third branches connected to two second recessed regions with an angle towards two sides outside the two first branches. The bottom-plate includes many female clip structures located at the first end, the second end, and the two sides. The apparatus includes a top-plate having corresponding male clip structures configured to lock with the female clip structures to at least have two shaped cavities at the first end for firmly holding fiber ferrules of the fiber-array substantially without lateral and axial motion while leaving excess lengths of fibers outside the second end.

Abstract: Apparatus and method for digital signal constellation transformation are provided herein. In certain configurations, an integrated circuit includes an analog front-end that converts an analog signal vector representing an optical signal into a digital signal vector, and a digital signal processing circuit that processes the digital signal vector to recover data from the optical signal. The digital signal processing circuit generates signal data representing a signal constellation of the digital signal vector. The digital signal processing circuit includes an adaptive gain equalizer that compensates the signal data for distortion of the signal constellation arising from biasing errors of optical modulators used to transmit the optical signal.

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

Abstract: A compact polarization beam splitter is formed by cascading two stages of three restricted MMIs. Each MMI is configured to set ultra compact width and length for a rectangular waveguide body to limit no more than 4 modes therein working as a polarization beam splitter in a 50 nm wavelength window around 1300 nm. Each MMI is further configured to couple an input at a first end and a TE bar output and a TM cross output at a second end of the rectangular waveguide body. The locations of the input/output waveguide ports are designated to be a distance of ? of the width away from a middle line from the first end to the second end. Two second-stage MMIs have their inputs coupled to the TE bar output and the TM cross output of the first-stage MMI and provide a second-stage TE bar output and a second-stage TM cross output, respectively.

Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a line driver with transistors directly coupled to the ground, and a bias voltage is coupled common mode resistors of the line driver. There are other embodiments as well.

Abstract: An apparatus for modulating a beam of light with balanced push-pull mechanism. The apparatus includes a first waveguide comprising a first PN junction on a silicon-on-insulator substrate and a second waveguide comprising a second PN junction on the silicon-on-insulator substrate. The second PN junction is a replica of the first PN junction shifted with a distance. The apparatus further includes a first source electrode and a first ground electrode coupled respectively with the first PN junction and a second source electrode and a second ground electrode coupled respectively with the second PN junction. The apparatus additionally includes a third ground electrode disposed near the second PN junction at the distance away from the second ground electrode, wherein the first ground electrode, the second ground electrode, and the third ground electrode are commonly grounded to have both PN junctions subjected to a substantially same electric field varied in ground-source-ground pattern.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: A computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and can include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. The plurality of rack modules can each include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.

Abstract: In an example, the present invention includes an integrated system on chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. In an example, the SerDes block is configured to convert a first data stream of N into a second data stream of M such that each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to the signal processing block.

Abstract: A transceiver for fiber optic communications.

Abstract: Embodiments are directed to a driver circuit for an electro-absorption modulator (EAM). Particular embodiments may employ a single differential electrical driver supplying complementary positive and negative voltage signals to two respective EAMs. DC bias for the EAMs is provided at a common node in the middle. An optical source is split and fed to each of the EAMs. The EAM receiving the positive voltage signal functions to communicate the optical data as output. The other EAM receiving the negative voltage is a dummy device providing a balance load for the differential driver circuit. Signal swing is determined by a termination resistor Rt located between parallel rails of the differential driver circuit. EAM properties such as swing and signal integrity can be traded off by choosing a different value for the termination resistor. In certain embodiments, the optical output of the dummy EAM may be used for device monitoring purposes.

Abstract: An optical communication system provides coherent optical transmission for metro applications. Relative to conventional solutions, the optical communication system can be implemented with reduced cost and can operate with reduced power consumption, while maintaining high data rate performance (e.g., 100 G). Furthermore, a programmable transceiver enables compatibility with a range of different types of optical networks having varying performance and power tradeoffs. In one embodiment, the optical communication system uses 100 Gb/s dual-polarization 16-point quadrature amplitude modulation (DP-16QAM) with non-linear pre-compensation of Indium Phosphide (InP) optics for low power consumption.