Abstract: A PAM4 driver with at least 56 Gbps speed for driving a Mach-Zehnder modulator. The PAM4 driver is configured as 2-bit CMOS digital-to-analog convertor including a drive control module for receiving a pair of incoming differential digital data and generating a first processed reference signal and a second processed reference signal. The PAM4 driver further includes a mirrored buffer circuit to produce two sets of four voltage levels. Furthermore, the PAM4 driver includes a decoder module controlled by a switch bias control module configured to decode each of the two sets of four voltage levels for generating a first output signal and a complementary second out signal with 4 independently adjustable analog levels for driving the Mach-Zehnder modulator with close ended termination resistor.

Abstract: In an example, the present invention includes an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: The present invention is directed to data communication. According to a specific embodiment, the present invention provides technique for loss of signal detection. A loss-of-signal detection (LOSD) device determines an analog signal indicating signal strength by subtracting a threshold offset voltage from an incoming signal. The analog signal is then processed by a switch network of an output stage circuit, which provides a digital output of loss of signal indication at a low frequency (relative to the incoming signal frequency). There are other embodiments as well.

Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.

Abstract: A Pulse Amplitude Modulated (PAM) optical device utilizing multiple wavelengths, features a communications interface having enhanced diagnostics capability. New registers are created to house additional diagnostic information, such as error rates. The diagnostic information may be stored in raw form, or as processed on-chip utilizing local resources.

Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.

Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.

Abstract: An optical transceiver by hybrid multichip integration. The optical transceiver includes a PCB with a plurality of prefabricated surface bonding sites. A first chip includes a FOWLP package of multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer is disposed on the PCB by respectively bonding a plurality of conductor balls between the dielectric redistribution layer and the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) in the dielectric molding layer. The optical transceiver further includes a second chip configured as a Sipho die comprising photonics devices embedded in a SOI wafer substantially free from any electronics device process. The second chip is stacked over the first chip with multiple conductor bumps being bonded respectively to the soldering material in the multiple TMVs.

Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

Abstract: Systems and methods described herein include methods and systems for controlling bias voltage provided to an optical modulating device. The optical modulating device is biased at a bias point that is different from a null point of the device such that an offset to the received optical power due to limited extinction ratio is reduced.

Abstract: A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.

Abstract: An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.

Abstract: The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a differential amplifier in cascode configuration. An input transistor is coupled to an output transistor via a peaking inductor. The output transistor is also directly coupled to a degeneration resistor. There are other embodiments as well.

Abstract: A clock phase detector circuit device and method. The device can include a first and second clock inputs connected to two pairs of transistors, each transistor having a first, second, and third terminal. The first pair includes a p-type transistor and n-type transistor configured such that the third terminals of each transistor are connected to form a first output node. Similarly, the second pair includes a p-type transistor and n-type transistor, the second p-type transistor and n-type transistor configured such that the third terminals of each transistor are connected to form a second output node. The first clock input is connected to the first terminals of the first p-type transistor and the second n-type transistor, while the second clock input is connected to the first terminals of the second p-type transistor and the first n-type transistor. As configured, the voltage outputs represent the phase difference between the clock inputs.

Abstract: The present invention is directed to communication systems and methods thereof. More specifically, an embodiment of the present invention includes a buffer that is coupled to a reference terminal. A shift register stores decision levels for post-cursor positions. A plurality of switches converts the decision levels to equalization currents during an equalization process. The equalization currents are converted to equalization voltage terms by one or more load resistors. The buffer is provided between the reference terminal and the one or more load resistors. There are other embodiments as well.

Abstract: When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.

Abstract: A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a ?3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption.

Abstract: An apparatus for converting fiber mode to waveguide mode. The apparatus includes a silicon substrate member and a dielectric member having an elongated body. Part of the elongated body from a back end overlies the silicon substrate member and remaining part of the elongated body up to a front end is separated from the silicon substrate member by a second dielectric material at an under region. The apparatus also includes a waveguide including a segment from the back end to a tail end formed on the dielectric member at least partially overlying the remaining part of the elongated body. The segment is buried in a cladding overlying entirely the dielectric member. The cladding has a refractive index that is less than the waveguide but includes an index-graded section with decreasing index that is formed at least over the segment from the tail end toward the back end.

Abstract: A receiver for fiber optic communications.