Abstract: Semiconductor arrangements and methods for manufacturing the same. The arrangement may include: a substrate; a back gate formed on the substrate; at least one pair of nanowires disposed on opposite sides of the back gate; and back gate dielectric layers interposed between the back gate and the respective nanowires.

Abstract: Semiconductor arrangements and methods for manufacturing the same are provided. In one embodiment, the arrangement may include: a semiconductor on insulator (SOI) substrate, comprising a base substrate, a buried dielectric layer, and a SOI layer; a back gate formed on the SOI substrate and passing through the buried dielectric layer to be in electric contact with the base substrate; fins formed from the SOI layer on opposite sides of the back gate; and back gate dielectric layers interposed between the back gate and the respective fins.

Abstract: A method for collecting a signal with a frequency lower than a Nyquist frequency includes, by a data transmitting end, selecting a suitable transformation base matrix for an input signal, deriving a sparse representation of the signal using the transformation base matrix to determine a sparsity of the signal, calculating a number M of compressive sampling operations according to the sparsity, sampling the signal with fNYQ/M using M channels, and integrating sampling values of each channel to obtain M measurement values. A reconstruction end reconstructs an original signal by solving optimization problems. Based on theory, compressive sampling can be performed on a sparse signal or a signal represented in a sparse manner with a frequency much lower than the Nyquist frequency, overcoming restrictions of the typical Nyquist sampling theorem. The method can be implemented simply and decrease pressure on data collection, storage, transmission and processing.

Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy.

Abstract: A semiconductor arrangement that includes: a substrate; a back gate formed on the substrate; fins formed on opposite sides of the back gate; and back gate dielectric layers interposed between the back gate and the respective fins. The back gate has opposite end portions recessed with respect to a middle portion thereof between the end portions, so that an overlap area between each of the end portions and each of the fins is smaller than an overlap area between the middle portion and the fin.

Abstract: A method of manufacturing a sub-wavelength extreme ultraviolet metal transmission grating is disclosed. In one aspect, the method comprises forming a silicon nitride self-supporting film window on a back surface of a silicon-based substrate having both surfaces polished, then spin-coating a silicon nitride film on a front surface of the substrate with an electron beam resist HSQ. Then, performing electron beam direct writing exposure on the HSQ, developing and fixing to form a plurality of grating line patterns and a ring pattern surrounding the grating line patterns. Then depositing a chrome material on the front surface of the substrate through magnetron sputtering. Then, removing the chrome material inside the ring pattern. Then, growing a gold material on the front surface of the substrate through atomic layer deposition.

Abstract: A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the device includes a multi-layer film formed by depositing alternating layers of insulation and an electrode material on a substrate. The device also includes through-holes formed by etching the film to the substrate. The device also includes gate stacks formed by depositing barrier storage and a tunnel layers in sequence on inner walls of the through-holes. The device also includes hollow channels formed by depositing a channel material on the tunnel layer. The device also includes drains for bit-line connection in top portions of the hollow channels. The device also includes sources formed in contact regions between through-holes and the substrate in bottom portions of the hollow channels.

Abstract: A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided.

Abstract: A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. An example method may include: forming a sacrificial gate stack on a substrate; forming a gate spacer on sidewalls of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack; partially etching back the sacrificial gate stack to form an opening; expanding the resultant opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer.

Abstract: A method for adjusting an effective work function of a metal gate. The method includes forming a metal gate arrangement comprising at least a metal work function layer, and performing plasma treatment on at least one layer in the metal gate arrangement. In this way, it is possible to adjust the effective work function of the metal gate in a relatively flexible way.

Abstract: The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of H2PtCl6 so as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt.

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device having silicon nitride with a tensile stress, the method comprising: c1) introducing and pre-stabilizing NH3 gas and N2 gas; c2) introducing silane; c3) igniting the gases by a radio-frequency source; c4) depositing SiN; and c5) processing the SiN by using a nitrogen ion implantation. According to the present disclosure, the nitrogen content in the SiN film can be enhanced by the nitrogen ion implantation and impinging, thereby increasing the density of the film. In this way, the acid resistance of the SiN with tensile stress is enhanced, so that the SiN with tensile stress may be integrated in a dual-strained liner of a gate-last process, so as to effectively improve the properties and reliability of the device.

Abstract: One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

Abstract: A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.

Abstract: In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located on the base region (100), and the base region (100) is supported on the substrate (130) by the support structure (131), wherein the sidewall cross-section of the support structure (131) is in a shape of a concave curve; an isolation structure (123) is formed beneath the edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and there exists a source/drain region at least on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.

Abstract: A semiconductor device and a method for manufacturing the same, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer to form an initial fin; performing anisotropic etching on the first semiconductor layer to form a ?-shaped lateral recess therein; forming an isolation layer on the substrate to have a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface located between a top surface and a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.