Abstract: Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

Abstract: A SRAM cell and a method for manufacturing the same are disclosed. In one embodiment, the SRAM cell may include: a semiconductor layer; and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the semiconductor layer, wherein the first FinFET includes a first fin formed by patterning the semiconductor layer, the first fin having a first top surface and a first bottom surface, wherein the second FinFET includes a second fin formed by patterning the semiconductor layer, the second fin having a second top surface and a second bottom surface, and wherein the first top surface is substantially flush with the second top surface, the first and second bottom surfaces abut against the semiconductor layer, and the height of the second fin is greater than the height of the first fin.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.

Abstract: One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

Abstract: The present disclosure discloses a method for manufacturing a P-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate diele

Abstract: Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.

Abstract: A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer on the substrate; forming a spacer on opposite sides of the sacrificial gate stack; and forming source/drain regions with the spacer as a mask.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate, which comprises, from top to bottom, an SOI layer (100), a BOX layer (110) and a base layer (130); forming a dummy gate stack on the SOI substrate and an implantation barrier layer on both sides of the dummy gate stack; removing the dummy gate stack to form a gate recess (220); and performing, via the gate recess (220), implantation of stress inducing ions to the semiconductor structure and annealing to form, right below the gate recess (220), a stress inducing region (150) under the BOX layer (110) of the SOI substrate. Accordingly, the present invention further provides a semiconductor structure manufactured according to the above method.

Abstract: A FinFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming a semiconductor fin having trapezoid cross-section. The method also includes forming one of a source region and a drain region. The method also includes forming a sacrificial spacer. The method also includes forming another one of the source region and the drain region using the sacrificial spacer as a mask. The method also includes removing the sacrificial spacer. The method also includes forming a gate stack in place of the sacrificial spacer, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin.

Abstract: A solid hole array and a method for forming the same are disclosed. The solid hold array may comprise: substrate with a via; a top hole array base formed on a top surface of the substrate and a bottom hole array base formed on a bottom surface of the substrate, wherein a front hole is located in the top hole array base at a place corresponding to the via; and top protection layer formed on a surface and sidewalls of the top hole array base and a bottom protection layer formed on a surface of the bottom hole array base, wherein a rear window is located in the bottom hole array base and the bottom protection layer at a place corresponding to the via.

Abstract: A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse a

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending along one direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings that span over the gate lines: c) implanting ions into the gate lines, such that the gate lines are insulated at the openings. The present invention enables the gate lines to maintain complete shape at formation of electrically isolated gates, which will not cause defects that exist in the prior art when forming a dielectric layers at subsequent steps, thereby guaranteeing performance of semiconductor devices. Additionally, the present invention further provides a semiconductor structure manufactured according to the method provided by the present invention.

Abstract: A low-noise and big tuning range voltage-controlled oscillator. Wherein a current source circuit is used for generating working current of the voltage-controlled oscillator, a resonance circuit is used for generating an oscillating signal of the voltage-controlled oscillator, the resonance circuit is an inductance and capacitance type resonance circuit, wherein capacitance adopts a metal oxide semiconductor (MOS) capacitive reactance tube or a reverse diode to increase the tuning range of the circuit, a negative resistance circuit is used for generating negative resistance to counteract positive resistance generated by the resonance circuit, and a feedback circuit is used for feeding back the oscillating signal generated by the resonance circuit to the current source circuit to add a new current to the current source so as to improve the use efficiency of the voltage controlled oscillator. Therefore, the voltage controlled oscillator has larger output voltage amplitude.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. In one aspect, the method comprises forming a first MOSFET having a first gate length in a semiconductor substrate, and forming a second MOSFET having a second gate length in the semiconductor substrate. Furthermore, the second gate length is less than the first gate length, and wherein the second MOSFET has a gate stack in the form of a spacer having a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor substrate.

Abstract: A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.

Abstract: A method for improving anti-radiation performance of SOI structure that includes implementing particle implantations of high-energy neutrons, protons and ?-rays to a buried oxide layer of an SOI structure, and then performing annealing process. The high-energy particle implantation introduces displacement damage to the buried oxide layer of the SOI structure.

Abstract: An FinFET and a method for manufacturing the same are disclosed. The FinFET comprises: a semiconductor substrate; a stress layer on the semiconductor substrate; a semiconductor fin on the stress layer, the semiconductor fin having two sidewalls extending in its length direction; a gate dielectric on the sidewalls of the semiconductor fin; a gate conductor on the gate dielectric; and a source region and a drain region at two ends of the semiconductor fin, wherein the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin.