Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench.

Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy.

Abstract: A method for manufacturing an NO2 gas sensor for detection at room temperature comprises: manufacturing a metal electrode on a surface of a flexible substrate; manufacturing an SWCNTs/SnO2 sensitive film; and bonding the SWCNTs/SnO2 sensitive film with a portion of the surface of the flexible substrate with the metal electrode, so as to form the NO2 gas sensor for detection at room temperature. The present disclosure solves the problems of the poor adhesion between the sensitive material and the flexible substrate, and a non-uniform distribution, and achieves the purposes of secure bonding between the sensitive material and the flexible substrate, and uniform distribution.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. In one aspect, the method includes forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate. The method also includes patterning the second and first semiconductor layers to form an initial fin. The method also includes selectively etching the first semiconductor layer of the initial fin to form a lateral recess in the first semiconductor layer. The method also includes filling the lateral recess with a dielectric material to form a body spacer. The method also includes forming an isolation layer on the substrate, wherein the isolation layer partially exposes the body spacer and thus defines a fin above the isolation layer. The method also includes forming a gate stack intersecting the fins on the isolation layer.

Abstract: The present disclosure provides a method for cleaning a lanthanum gallium silicate wafer which comprises the following steps: at a step of 1, a cleaning solution constituted of phosphorous acid, hydrogen peroxide and deionized water is utilized to clean the lanthanum gallium silicate wafer with a megahertz sound wave; at a step of 2, the cleaned lanthanum gallium silicate wafer is rinsed and dried by spinning; at a step of 3, a cleaning solution constituted of ammonia, hydrogen peroxide and deionized water is utilized to clean the lanthanum gallium silicate wafer with the megahertz sound wave; at a step of 4, the cleaned lanthanum gallium silicate wafer is rinsed and dried by spinning; and at a step of 5, the rinsed and dried wafer is placed in an oven to be baked.

Abstract: A defect detection system for an extreme ultraviolet lithography mask comprises an extreme ultraviolet light source (1), extreme ultraviolet light transmission parts (2, 3), an extreme ultraviolet lithography mask (4), a photon sieve (6) and a collection (7) and analysis (8) system. Point light source beams emitted by the extreme ultraviolet light source (1) are focused on the extreme ultraviolet lithography mask (4) through the extreme ultraviolet light transmission parts (2, 3); the extreme ultraviolet lithography mask (4) emits scattered light and illuminates the photon sieve (6); and the photon sieve (6) forms a dark field image and transmits the same to the collection (7) and analysis (8) system. The defect detection system for the extreme ultraviolet photolithographic mask uses the photon sieve to replace a Schwarzchild objective, thereby realizing lower cost, relatively small size and high resolution.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure.

Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

Abstract: A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor which includes: an oxide substrate; an oxide film on the oxide substrate, wherein an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxide film and electrically connected with the interfacial layer; a front gate on the oxide film; and a back gate on a lower surface of the oxide substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a first gate dielectric layer and floating gate layer; forming a mask layer as a spacer on a sidewall of a remaining portion of the second shielding layer, and patterning the floating gate layer with the mask layer as a mask, and then removing the mask layer; and forming a second gate dielectric layer, and forming a gate conductor as a spacer on the sidewall of the remaining portion of the second shielding layer.

Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure contains carbon-based materials; forming source/drain region in the substrate on both sides of the dummy gate stack structure; performing etching to remove the dummy gate stack structure until the substrate is exposed, resulting in a gate trench; and forming a gate stack structure in the gate trench. In accordance with the method for manufacturing a semiconductor device of the present invention, the dummy gate made of carbon-based materials is used to substitute the dummy gate made of silicon-based materials, then no oxide liner and/or etch blocking layer needs be added while the dummy gate is removed by etching in the gate last process, thus the reliability of device is ensured while the process is simplified and the cost is reduced.

Abstract: A semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; forming an isolation layer on the substrate, wherein the isolation layer exposes partially the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer, wherein the first semiconductor layer comprises a compound semiconductor, with at least one component whose concentration has a graded distribution in a stack direction of the first and second semiconductor layers.

Abstract: The present disclosure provides a millimeter-wave waveguide communication system. The millimeter-wave waveguide communication system may comprise: a clock component, and at least two sets of millimeter-wave receiving/transmitting channels. The clock component is configured to provide a clock signal to sending ends and receiving ends of the two sets of millimeter-wave receiving/sending channels respectively. Each set of millimeter-wave receiving/sending channels comprises: a transmitter component, a receiver component and a transmission waveguide. The transmission waveguide is located between the transmitter component and the receiver component and is configured to provide a channel for millimeter-wave transmission. The top face, side face and/or bottom face of the transmission waveguide, except for active devices and accessories thereof, are plated with a metal conductive wall to form an electromagnetic shield from a transmission waveguide in an adjacent millimeter-wave receiving/sending channel.

Abstract: There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer on the fin; d. forming a shallow trench isolation on both sides of the fin; e. forming a sacrificial gate stack and a spacer on the top surface and sidewalls of the channel region which is in the middle of the fin; f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack; h. removing the sacrificial gate stack stack to form a sacrificial gate vacancy and expose the channel region and the channel protective layer; i. covering a portion of the semiconductor structure in one end of the fin with a photoresist layer; j. removing a portion of the spacer not covered; k. removing the photoresist layer and filling a gate stack in the sacrificial gate vacancy; l.

Abstract: A radio frequency (RF) power source having a precise power detector includes a RF signal generator, a RF power amplifying circuit, a power supply circuit, and a precise power detector. The precise power detector includes a voltage mutual inductor, a current mutual inductor, a precise detecting module, and a microcontroller integrated with an analog-digital (A/D) converter and a micro-processing unit, wherein the voltage mutual inductor and the current mutual inductor are respectively connected with the precise detecting module. The precise detecting module includes an add circuit, a subtraction circuit, a rectification circuit, and a filtering-amplifying circuit, wherein the add circuit and the subtraction circuit are respectively connected with the rectification circuit, the rectification circuit connects to the filtering-amplifying circuit, the filtering-amplifying circuit connects to the microcontroller integrated with the A/D converter and the micro-processing unit.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a substrate having a well formed therein, the well including a first section and a second section, wherein the first section has a lower doping concentration and is closer to a surface of the substrate than the second section; a fin structure formed on the surface of the substrate; an isolation layer formed on the surface of the substrate, wherein the isolation layer exposes a portion of the fin structure, which serves as a fin for the semiconductor device; a gate stack formed on the isolation layer and intersecting the fin, wherein a Punch-Through Stopper (PTS) is formed in only a region directly under a portion of the fin where the fin intersects the gate stack.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

Abstract: A MOSFET and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100), a dummy gate structure (200), a epitaxial protection layer (101) and a sacrificial spacer (205); b. covering the dummy gate structure (200) and the substrate (100) on one side thereof by a mask layer, and forming a vacancy (102) in the substrate; c. growing a semiconductor layer (300) on the semiconductor structure to fill in the vacancy (102); d. removing the epitaxial protection layer (101) and the sacrificial spacer (205), and sequentially forming source/drain extension regions, a spacer (201), source/drain regions, and an interlayer dielectric layer (500); and e. removing the dummy gate structure (200) to form a dummy gate vacancy, and forming a gate stack in the dummy gate vacancy. In the MOSFET structure of the present disclosure, negative effects of DIBL on device performance can be effectively reduced.

Abstract: A TI-IGBT, comprising a first semiconductor substrate, a second semiconductor substrate, and a first doped layer; a short circuit region and a collector region disposed in parallel are formed in the first semiconductor substrate; the short circuit region and the collector region have different doping types; the second semiconductor substrate is located on the upper surface of the first semiconductor substrate, and has the same doping type with the short circuit region; the first doped layer is located between the first semiconductor substrate and the second semiconductor substrate, and covers at least the collector region; the first doped layer has the same doping type with the second semiconductor substrate, and has a doping concentration smaller than that of the second semiconductor substrate.