Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a drain region in the substrate on one side of the gate stack structure; and forming a source region made of GeSn in the substrate on the other side of the gate stack structure; wherein the forming the source region made of GeSn comprises: implanting precursors in the substrate on the other side of the gate stack structure; and performing a laser rapid annealing such that the precursors react to produce GeSn alloy, thereby to constitute a source region; and wherein the step of implanting precursors further comprises: performing a pre-amorphization ion implantation, so as to form an amorphized region in the substrate; and implanting Sn in the amorphized region.

Abstract: A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method.

Abstract: This invention provides a load-balancing structure for packet switches and its constructing method. In this method, the structure based on self-routing concentrators is divided into two stages, that is, a first stage and a second stage fabric. A virtual output group queue (VOGQ) is appended to each input group port of the first stage fabric, and a reordering buffer (RB) is configured behind each output group port of the second stage fabric. Packets stored in the VOGQ are combined into data blocks with preset length, which is divided into data slices of fixed size, finally each data slice is added an address tag and is delivered to the first stage fabric for self-routing. Once reaching the RB, data slices are recombined into data blocks. This invention solves the packet out-of-sequence problem in the load-balancing Birkhoff-von Neumann switching structure and improves the end-to-end throughput.

Abstract: A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.

Abstract: The invention provides a semiconductor device, including: a semiconductor base, on an insulation layer; source/drain regions abutting opposite first sides of the semiconductor base; and gates at opposite second sides of the semiconductor base, wherein the semiconductor base includes a cavity, and the insulation layer is exposed by the cavity. The invention also provides a method for forming a semiconductor device, including: forming a semiconductor bottom on an insulation layer; forming source/drain regions, the source/drain regions abutting opposite first sides of the semiconductor bottom; forming gates on opposite second sides of the semiconductor bottom; and removing a part of the semiconductor bottom to form a cavity in the semiconductor bottom, the cavity exposing the insulation layer. With the technical solutions provided by the invention, short-channel effects can be alleviated, and the resistance of the source/drain regions and parasitic capacitance can be reduced.

Abstract: The present application discloses a semiconductor Field-Effect Transistor (FET) structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising an SOI structure having a body-contact hole; forming a fin on the SOI structure of the semiconductor substrate; forming a gate stack structure on top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof becomes simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated; the present invention also is favorable for suppressing short channel effects desirably, and boosts MOSFETs to develop towards a trend of downscaling size.

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a dielectric layer on the substrate and the gate stack; performing a main etching operation on the dielectric layer to form a spacer, with a remainder of the dielectric layer left on the substrate; and performing an over etching operation to remove the remainder of the dielectric layer. According to the method disclosed herein, two etching operations where an etching gas comprises a helium gas are performed, without forming an etching stop layer of silicon oxide. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.

Abstract: The present application discloses a voltage-controlled oscillator device and a method of correcting the voltage-controlled oscillator. The voltage-controlled oscillator device comprises predistortion module, configured to predistort an input voltage to obtain a predistorted voltage; and a voltage-controlled oscillator, configured to generate an output signal with a corresponding oscillation frequency according to the predistorted voltage, wherein the predistortion module corrects a non-linear characteristic of the voltage-controlled oscillator, so that there is a linear relationship between the input voltage and the oscillation frequency of the output signal. The voltage-controlled oscillator device may be applied to a phase-locked circuit in a communication system.

Abstract: The present invention provides a FinFET flash memory device and the method for manufacturing the same. The flash memory device is on an insulating layer, comprising: a first fin and a second fin, wherein the second fin is a control gate of the device; a gate dielectric layer, at side walls and top of the first fin and the second fin; source/drain regions, inside the first fin at both sides of a floating gate.

Abstract: An in-situ fabrication method for a silicon solar cell includes the following steps: pretreating a silicon chip; placing the pretreated silicon chip in an implantation chamber of a plasma immersion ion implantation machine; completing the preparation of black silicon via a plasma immersion ion implantation process; making a PN junction and forming a passivation layer on the black silicon; after making the PN junction and forming the passivation layer, removing the black silicon from the plasma immersion ion implantation machine; preparing a metal back electrode on the back of the black silicon; preparing a metal grid on the passivation layer; obtaining a solar cell after encapsulation. Said method enables black silicon preparation, PN junction preparation, and passivation layer formation in-situ, greatly reducing the amount of equipment needed for the preparation of solar cells and the preparation cost. In addition, the method is simple and easy to control.

Abstract: Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer; then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate.

Abstract: The present invention discloses a method for manufacturing a semiconductor device comprising the steps of: forming a plurality of source and drain regions in a substrate; forming a plurality of gate spacer structures and an interlayer dielectric layer around the gate spacer structures on the substrate, wherein the gate spacer structures enclose a plurality of first gate trenches and a plurality of second gate trenches; sequentially depositing a first gate insulating layer and a second gate insulating layer, a first blocking layer and a second work function regulating layer in the first and second gate trenches; performing selective etching to remove the second work function regulating layer from the first gate trenches to expose the first blocking layer; depositing a first work function regulating layer on the first blocking layer in the first gate trenches and on the second work function regulating layer in the second gate trenches; and depositing a resistance regulating layer on the first work function regu

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first space

Abstract: The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.

Abstract: A water transfer apparatus and a wafer transfer method are provided. The wafer transfer apparatus is provided with a heating component and a cooling component, the heating component heats the wafer carrying component to a temperature the same as the wafer when it is just unloaded from the rapid thermal anneal tool, and the cooling component cools the wafer carrying component along with the wafer to room temperature, thereby avoiding the large temperature difference between the wafer and the wafer transfer apparatus, preventing the high thermal stress induced inside the wafer during wafer transfer, avoiding wafer breakage, and ensuring the completeness of the wafer.

Abstract: A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region to increase carrier mobility and improve performances of the device.