Abstract: The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal.

Abstract: A detector based on a gallium nitride-based enhancement-mode device and a manufacturing method thereof. The detector is a gas or solution detector. When the detector is used in electrolyte solution detection, electrolyte solution is located in the gate opening region and directly contacts the thin barrier layer to form a contact interface. The electrolyte solution affects interface charges at the contact interface, leading to a change in a concentration of the two-dimensional electron gas, and further a change in a current between the source and the drain. When the detector is used in a hydrogen-containing gas detection, the H concentration of the hydrogen-containing gas affects interface charges at the contact interface between the gate and the thin barrier layer, leading to a change in a concentration of the two-dimensional electron gas, and further a change in the current between the source and the drain.

Abstract: A semiconductor device, a method of manufacturing the same and an electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device may include a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence on the substrate, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a channel region close to its peripheral surface and a body region disposed on an inner side of the channel region.

Abstract: Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

Abstract: A field emission cathode electron source and an array thereof provided by embodiments of the present disclosure include a substrate, and a cathode, a cathode tip and a gate disposed on the same side of the substrate. The cathode, the cathode tip and the gate are disposed on an upper surface of the substrate, and the cathode tip is connected to the cathode, and the gate is located on a side of the cathode tip away from the cathode and an electron emission end of the cathode tip is directed toward a side of the substrate close to the gate. The cathode tips are arranged on the substrate in parallel with the substrate. Compared with the three dimensional stacked structure in the prior art, the present disclosure has a higher stability and reliability and is suitable for a large-scale integration.

Abstract: A semiconductor arrangement includes: a substrate; a plurality of fins formed on the substrate and extending in a first direction; a plurality of gate stacks formed on the substrate and extending in a second direction crossing the first direction and dummy gates composed of dielectric and extending in the second direction, wherein each of the gate stacks intersects at least one of the fins; and spacers formed on sidewalls of the gate stacks and sidewalls of the dummy gates, wherein spacers of at least a first one and a second one among the gate stacks and the dummy gates which are aligned in the second direction extend integrally, and at least some of the fins have ends abutting the dummy gates and substantially aligned with inner walls of corresponding ones of the spacers.

Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.

Abstract: There are provided a multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same. The FinFET may include a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.

Abstract: A method of manufacturing a grooved-gate MOSFET device based on a two-step microwave plasma oxidation, including: etching a grooved gate, and oxidizing silicon carbide on a surface of the grooved gate to silicon dioxide by microwave plasma to form a grooved-gate oxide layer, the step of forming the grooved-gate oxide layer including: placing a silicon carbide substrate subjected to the grooved gate etching in a microwave plasma generating device; introducing a first oxygen-containing gas, heating generated oxygen plasma to a first temperature at a first heating rate, and performing low-temperature plasma oxidation at the first temperature and a first pressure; heating the oxygen plasma to a second temperature at a second heating rate, introducing a second oxygen-containing gas, and performing high-temperature plasma oxidation at the second temperature and a second pressure until a predetermined thickness of silicon dioxide is formed; stopping introduction of the oxygen-containing gas, and completing the react

Abstract: A magnetoresistive random access memory and a method for manufacturing the same are provided, with which a stress layer covers a part of the protective layer along a direction of a current in the spin-orbit coupling layer, so that a stress is generated on the part of the magnetic layer locally due to the stress layer, thus a lateral asymmetric structure is formed in a direction perpendicular to the current source. In a case that a current is supplied to the spin-orbit coupling layer, the spin-orbit coupling effect in the magnetic layer is asymmetric due to the stress on the part of the magnetic layer, thereby realizing a deterministic switching of the magnetic moment under the function of the stress.

Abstract: A GaN-based enhancement-mode power electronic device and a method for manufacturing the same. The GaN-based enhancement-mode power electronic device comprises: a substrate; a thin barrier Al(In,Ga)N/GaN heterostructure formed on the substrate; a gate, a source, and a drain formed on the thin barrier Al(In,Ga)N/GaN heterostructure. An AlN or SiNx passivation layer is formed on access regions between the gate and the source and between the gate and the drain, respectively, such that two dimensional electron gas is recovered in channels of the thin barrier Al(In,Ga)N/GaN heterostructure below the MN passivation layer by utilizing the MN passivation layer having polarization characteristics, or by using the SiNx passivation layer with positive fixed bulk/interface charges, so as to reduce on-resistance of the device and inhibit high-voltage current collapse in the device.

Abstract: A microwave plasma equipment and a method of exciting plasma are disclosed. The microwave plasma equipment includes: a plasma reaction device having a cavity in which a base support and a plasma-forming area is provided; a conversion device having gradient electrodes, the gradient electrodes being disposed inside the cavity and configured to generate a gradient electric field in the plasma-forming area; a gas supply device configured to introduce gas into the cavity of the plasma reaction device; and a microwave generating device configured to generate and transmit microwave into the cavity of the plasma reaction device.

Abstract: A microwave plasma generating device for plasma oxidation of SiC, comprising an outer cavity and a plurality of micro-hole/micro-nano-structured double-coupling resonant cavities disposed in the outer cavity. Each resonant cavity includes a cylindrical cavity. A micro-hole array formed by a plurality of micro-holes is uniformly distributed on a peripheral wall of the cylindrical cavity, a diameter of each of the micro-holes is an odd multiple of wavelength, and an inner wall of the cylindrical cavity has a metal micro-nano structure, the metal micro-nano structure has a periodic dimension of ?/n, where ? is wavelength of an incident wave, and n is refractive index of material of the resonant cavity. The outer cavity is provided with an gas inlet for conveying an oxygen-containing gas into the outer cavity, and the oxygen-containing gas forms an oxygen plasma around the resonant cavities for oxidizing SiC; a stage is disposed under the resonant cavities.

Abstract: Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer.

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.

Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: performing composition and a chemical combination treatment on a lower copper electrode (10) to generate a compound buffer layer (40), wherein the compound buffer layer (40) is capable of preventing the oxidation of the lower copper electrode (10); depositing a solid electrolyte material (50) on the compound buffer layer (40); and depositing an upper electrode (60) on the solid electrolyte material (50) to form the memory.

Abstract: A spin-orbit torque magnetoresistive random access memory, and a method for manufacturing a spin-orbit torque magnetoresistive random access memory are provided. The spin-orbit torque magnetoresistive random access memory includes a spin-orbit coupling layer and a magnetoresistive tunnel junction located on the spin-orbit coupling layer. The magnetoresistive tunnel junction includes a first magnetic layer, a tunneling layer, and a second magnetic layer that are sequentially stacked from bottom to top, and each of the first magnetic layer and the second magnetic layer has perpendicular anisotropy. In a direction of a current in the spin-orbit coupling layer, defects are generated in a part of the magnetoresistive tunnel junction by an ion implantation process.