Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: performing composition and a chemical combination treatment on a lower copper electrode (10) to generate a compound buffer layer (40), wherein the compound buffer layer (40) is capable of preventing the oxidation of the lower copper electrode (10); depositing a solid electrolyte material (50) on the compound buffer layer (40); and depositing an upper electrode (60) on the solid electrolyte material (50) to form the memory.

Abstract: An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.

Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffu

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Abstract: A nonvolatile resistive switching memory includes an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode. A graphene intercalation layer with nanopores, interposed between the easily oxidizable metal electrode and the resistive switching functional layer, is capable of controlling the metal ions, which are formed by the oxidation of the easily oxidizable metal electrode during the programming of the device, and only enter into the resistive switching functional layer through the position of the nanopores. Further, the graphene intercalation layer with nanopores is capable of blocking the diffusion of the metal ions, making the metal ions, which are formed after the oxidation of the easily oxidizable metal electrode, enter into the resistive switching functional layer only through the position of the nanopores during the programming of the device, thereby controlling the growing position of conductive filament.

Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. An example semiconductor device may include: a Semiconductor on Insulator (SOI) substrate, including a base substrate, a buried dielectric layer and an SOI layer, an active area disposed on the SOI substrate and including a first sub-area and a second sub-area, wherein the first sub-area includes a first fin portion, the second sub-area includes a second fin portion opposite to the first fin portion, and at least one of the first sub-area and the second sub-area includes a laterally extending portion; a back gate arranged between the first fin portion and the second fin portion; back gate dielectric layers sandwiched between the back gate and the respective fin portions; and a gate stack formed on the active area.

Abstract: A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.

Abstract: The present disclosure relates to the technical field of information data storage and processing. There is provided a method for regulating magnetic multi-domain state, comprising: when a current is applied to a magnetic thin film, applying an additional external magnetic field having a magnetic field strength of 0 to 4×105 A/m to regulate magnetization state of the magnetic thin film; wherein the current is configured to drive movements of a magnetic domain of the magnetic multi-domain states in the magnetic thin film, and the external magnetic field is configured to regulate generation of new magnetic domain in the magnetic thin film and state of the magnetic domain during the movement, so that the magnetic thin film is in a stable magnetic multi-domain state. Such a multi-domain state can't be affected by a higher or lower current and keeps stable when the current is removed.

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

Abstract: Provided are a semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate, wherein the first semiconductor layer is doped; patterning the second and first semiconductor layers to form an initial fin; forming a dielectric layer on the substrate to substantially cover the initial fin, wherein a portion of the dielectric layer on top of the initial fin has a thickness sufficiently less than that of a portion of the dielectric layer on the substrate; etching the dielectric layer back to form an isolation layer, wherein the isolation layer partially exposes the first semiconductor layer, thereby defining a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.

Abstract: Memory devices, methods of manufacturing the same, and methods of accessing the same are provided. In one embodiment, the memory device may include a substrate, a back gate formed on the substrate, and a transistor. The transistor may include fins formed on opposite sides of the back gate on the substrate and a gate stack formed on the substrate and intersecting the fins. The memory device may further include a back gate dielectric layer formed on side and bottom surfaces of the back gate. The back gate dielectric layer may have a thickness reduced portion at a region facing the fins on one side of the gate stack.

Abstract: A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.

Abstract: Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.

Abstract: There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.

Abstract: Planarization processing methods are disclosed. In one aspect, the method includes patterning a material layer and planarizing the patterned material layer by using sputtering. Due to the patterning of the material layer, the loading requirements of nonuniformity on a substrate for sputtering the material layer are reduced, compared with that before the patterning.

Abstract: The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region.

Abstract: The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device.

Abstract: A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.