Patents Assigned to Institute of Microelectronics
  • Patent number: 11373948
    Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 28, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11366946
    Abstract: The present disclosure provides a method and an apparatus for obtaining surface potential.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: June 21, 2022
    Assignee: THE INSTITUTE OF MICROELECTRONICS OF CHINESE ACADEMY OF SCIENCES
    Inventors: Nianduan Lu, Ling Li, Ming Liu
  • Patent number: 11361799
    Abstract: A semiconductor memory device including a substrate; an array of memory cells arranged in rows and columns on the substrate, each memory cell comprising a vertical pillar-shaped active region having upper and lower source/drain regions and a channel region, and a gate stack formed around the channel region; a plurality of bit lines on the substrate, each bit line located below a column of memory cells and electrically connected to the lower source/drain regions of the memory cells; and a plurality of word lines on the substrate, each word line extending in a row direction and connected to gate conductors of the memory cells in a row of memory cells, each word line comprising first portions extending along peripheries of the memory cells and second portions extending between the first portions, the first portions of the word line extending in a conformal manner with sidewalls of the upper source/drain regions.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 14, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11329149
    Abstract: There are provided a vertical semiconductor device, a method of manufacturing the same, and an electronic device including the same.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 10, 2022
    Assignee: Institute of Microelectronics, The Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11309432
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 19, 2022
    Assignee: Institute of Microelectronics, Chinese /Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11289499
    Abstract: A memory device may include first and second pillar-shaped active regions formed on a substrate and extending upward. The first and second active regions are arranged in a first array and a second array, respectively. Each of the first active regions comprises alternatively stacked source/drain layers and channel layers, wherein the channel layers of the respective first active regions at a corresponding level are substantially coplanar with each other, and the source/drain layers of the respective first active regions at a corresponding level are substantially coplanar with each other. Each of the second active regions comprises an active semiconductor layer extending integrally. The memory device may include multiple layers of first storage gate stacks surrounding peripheries of and being substantially coplanar with the respective levels of the channel layers, and multiple layers of second storage gate stacks which surround peripheries of the respective second active regions.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 29, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11289594
    Abstract: A GaN-based superjunction vertical power transistor and a manufacturing method thereof. The transistor includes: a N?-GaN layer; a first P-GaN layer as a current blocking layer, formed on the N?-GaN layer and having a gate region window; and a thin barrier Al(In, Ga)N/GaN heterostructure conformally formed on the current blocking layer and filling the bottom and one or more sidewalls of the gate region window, wherein the N?-GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, an N+-GaN layer is formed under the second P-type GaN layer, and the N+-GaN layer is in direct contact with the second P-type GaN layer and the N?-GaN layer to form a superjunction composite structure.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 29, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Sen Huang, Xinhua Wang, Xinyu Liu, Yuankun Wang, Haibo Yin, Ke Wei
  • Patent number: 11276769
    Abstract: A method of manufacturing a semiconductor device may include: forming a fin-shaped structure on a substrate; forming a supporting layer on the substrate having the fin-shaped structure formed thereon, and patterning the supporting layer into a supporting portion extending from a surface of the substrate to a surface of the fin-shaped structure and thus physically connecting them; removing a portion of the fin-shaped structure close to the substrate to form a first semiconductor layer spaced apart from the substrate; growing a second semiconductor layer with the first semiconductor layer as a seed layer; and in at least a fraction of the longitudinal extent, removing the first semiconductor layer, and cutting off the second semiconductor layer on sides of the first semiconductor layer away from the substrate and close to the substrate, respectively, so that the cut-off second semiconductor layer acts as a fin of the device.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 15, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11257933
    Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is formed on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 22, 2022
    Assignee: Institute of Microelectronics, Chinese Academy
    Inventors: Huaxiang Yin, Qingzhu Zhang, Renren Xu
  • Patent number: 11251184
    Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 15, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Yanbo Zhang, Huicai Zhong
  • Patent number: 11251183
    Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 15, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Yanbo Zhang, Huicai Zhong
  • Patent number: 11245035
    Abstract: A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: February 8, 2022
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 11245074
    Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: February 8, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Hangbing Lv, Ming Liu, Shibing Long, Qi Liu
  • Patent number: 11223013
    Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: January 11, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Qi Liu, Xiaolong Zhao, Sen Liu, Ming Liu, Hangbing Lv, Shibing Long, Yan Wang, Facai Wu
  • Patent number: 11215652
    Abstract: A method for obtaining a contact resistance of a planar device includes: obtaining a contact resistance of a planar device by using a potential measurement method, in the measurement of the surface potential distribution, the planar device is in a state of current flowing, a certain voltage drop is formed at a junction area of the device; extracting the voltage drop measured through the Kelvin microscope by using a linear fitting method; and dividing the measured voltage drop by the current flowing through the device, thereby accurately calculating the magnitude of the contact resistance at the junction area of the planar device. With the present invention, the contact resistance of the planar device can be precisely measured, which is suitable for the contact resistance measurement experiments of devices such as thin film transistors and diodes.
    Type: Grant
    Filed: December 25, 2015
    Date of Patent: January 4, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Guangwei Xu, Zhiheng Han, Wei Wang, Congyan Lu, Lingfei Wang, Ling Li, Ming Liu
  • Patent number: 11217493
    Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: January 4, 2022
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11205750
    Abstract: The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: December 21, 2021
    Assignee: Institute of Microelectronics Chinese Academy of Sciences
    Inventors: Qing Luo, Hangbing Lv, Ming Liu, Xiaoxin Xu, Cheng Lu
  • Patent number: 11195765
    Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar with each other, and the respective second source/drain layers of the first device and the second device are stressed differently.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 7, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11189345
    Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 30, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Qi Liu, Wei Wang, Sen Liu, Feng Zhang, Hangbing Lv, Shibing Long, Ming Liu
  • Publication number: 20210344115
    Abstract: The present invention relates to an integration module system of millimeter-wave and non-millimeter-wave antennas and an electronic apparatus, the system comprising a millimeter-wave antenna module and a non-millimeter-wave environment, the millimeter-wave antenna module forming a communication connection with the non-millimeter-wave environment for realizing reusing of the millimeter-wave antenna module to achieve a function of non-millimeter-wave antenna(s). The present invention proposes directly reusing a millimeter-wave antenna module, which is designed so that this module also has an antenna function of a non-millimeter-wave module, while an individual module's own volume does not need to be increased, and the module itself does not need to have additionally-added antenna traces, that is, with the same volume, a function of non-millimeter-wave antenna(s) may be further added.
    Type: Application
    Filed: June 30, 2020
    Publication date: November 4, 2021
    Applicants: ETHETA COMMUNICATION TECHNOLOGY (SHENZHEN) CO.,LTD, EAST CHINA RESEARCH INSTITUTE OF MICROELECTRONICS
    Inventors: Huan-Chu HUANG, Jiaguo LU, Hong LIN, Junyong LIU, Zhixing QI, Minhui ZENG, Yanchao ZHOU, Jingwei LI, Tao MA